EP0135121A1 - Montage pour la génération de signaux rectangulaires - Google Patents

Montage pour la génération de signaux rectangulaires Download PDF

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Publication number
EP0135121A1
EP0135121A1 EP84109510A EP84109510A EP0135121A1 EP 0135121 A1 EP0135121 A1 EP 0135121A1 EP 84109510 A EP84109510 A EP 84109510A EP 84109510 A EP84109510 A EP 84109510A EP 0135121 A1 EP0135121 A1 EP 0135121A1
Authority
EP
European Patent Office
Prior art keywords
circuit arrangement
flip
flop
reset
square
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP84109510A
Other languages
German (de)
English (en)
Other versions
EP0135121B1 (fr
Inventor
Helmut Dipl.-Ing. Fischer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to AT84109510T priority Critical patent/ATE26370T1/de
Publication of EP0135121A1 publication Critical patent/EP0135121A1/fr
Application granted granted Critical
Publication of EP0135121B1 publication Critical patent/EP0135121B1/fr
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/015—Modifications of generator to maintain energy constant
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0232—Monostable circuits
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/24—Pc safety
    • G05B2219/24032—Power on reset, powering up

Definitions

  • the invention relates to a circuit arrangement for generating square-wave signals in accordance with the preamble of patent claim 1.
  • the voltage on the first capacitor during the subsequent charging determines the point in time at which the second capacitor changes from the discharging to the charging state. This threshold voltage therefore goes directly into the tolerances of the circuit.
  • the known circuit is well suited to follow the changes in the repetition frequency of the input signals, but there is no compensation for short-term fluctuations in the repetition frequency.
  • synchronization circuits are generally known which use, for example, integrated circuits which are commercially available as so-called "phase locked loops". These synchronizing circuits generate square-wave signals that match the input signals in terms of phase and frequency. However, they do require a relatively large effort, since they include, for example, an oscillator that generates the square-wave signals and whose repetition frequency is changed depending on the phase difference between the square-wave signals and the input signals.
  • the invention is therefore based on the object of specifying a further developed circuit arrangement for generating square-wave signals, the repetition frequency of which corresponds to the repetition frequency of the input signals and the pulse duty factor is constant.
  • This circuit arrangement should also have a high degree of synchronization capability, particularly in the case of discontinuous operation, i.e. have a stable starting behavior that is largely independent of the initial state when switching on.
  • the circuit arrangement according to the invention is characterized in particular by the fact that a regulated response threshold is introduced, which is implemented by the first integrating element.
  • This threshold value determining the function of the comparator depends directly on the repetition frequency and varies in accordance with the changes in the repetition frequency. This ensures that the circuit arrangement quickly re-centers itself and remains capable of synchronization even in the event of sudden changes in the repetition frequency.
  • the circuit arrangement according to the invention has the further advantage that it is still very inexpensive can be built. It can be constructed inexpensively, in particular in the form of a thick-film or thin-film circuit.
  • the circuit arrangement has a constant pulse duty factor in a relatively large frequency range.
  • capacitors are provided as the first and second integrating elements. Instead of the capacitors, it is also conceivable to provide counters which are counted up or down by counting clocks of constant repetition frequency or which are counted up and reset.
  • the comparator can also be designed as a digital comparator, so that the circuit arrangement can be produced exclusively from integrated circuits.
  • the circuit arrangement shown in FIG. 1 contains a flip-flop F, a changeover switch US, two integrators I1 and 12, a switch S, three current sources ST1 - to ST3 and a comparator K.
  • the integrators I1 and 12 are capacitors C1 and C2 educated.
  • Input signals E are present at the flip-flop F at a set input and the flip-flop F outputs the square-wave signals R at its output.
  • the time t is shown in the abscissa direction and instantaneous values of signals in the ordinate direction at various points in the circuit arrangement.
  • the flip-flop F is set.
  • the square-wave signal R at its output assumes the binary value 1 and brings the changeover switch US to the position 2.
  • the capacitor C1 which has the instantaneous value SW as a voltage value, is discharged via the current source ST2 with a relatively large time constant.
  • the square-wave signal R opens the switch S, so that the capacitor C2 is charged via the current source ST3. This charging takes place with a smaller time constant than the discharge of the capacitor C1.
  • the comparator K determines that the instantaneous value SW on the capacitor C1 corresponds to the instantaneous value AS and sets with a reset signal RS the flip-flop F back.
  • the square wave signal R assumes the binary value 0, as a result of which the changeover switch US is brought into position 1 and the switch S is closed.
  • the capacitor C2 is immediately discharged and kept in the discharged state.
  • the capacitor C1 is charged using the current source ST1 with a relatively large time constant.
  • the square-wave signals R have a duty cycle of 1: 2, i.e. the pulse / pause ratio is 1: 1.
  • Any duty cycle or pulse / pause ratio can be set by changing the current sources ST1 and ST2. This duty cycle or pulse / pause ratio is always constant regardless of the repetition frequency of the input signals E.
  • the repetition frequency of the input signals E increases, the time period between 1-5 and t4 during which the capacitor C1 is discharged is greater than the time period between the times t6 and t5 during which the capacitor C1 is recharged that the voltage across capacitor C1 becomes lower.
  • the comparator K thus determines the correspondence between the instantaneous values SW and AS earlier at the time t7, so that the flip-flop F is reset earlier and the same pulse duty factor is restored after a short transient. Similar processes are repeated between times t8 and t9 as between times t6 and t8.
  • the square-wave signal R is emitted at the non-inverting output of the flip-flop F.
  • this flip-flop F has an output in which the output transistor has no collector resistor.
  • a transistor T2 forms, together with resistors R1 and R2, a constant current source corresponding to the current source ST2, which discharges the capacitor C1 serving as an integrating element I1.
  • a transistor T1 together with resistors R3 to R5 forms a constant current source corresponding to the current source ST1, which charges the capacitor C1.
  • the resistors R1 to R5 are dimensioned such that the resulting discharge current of the capacitor C1 is just as large as the charge current in the event that the transistor T2 is blocked.
  • the dynamic readjustment behavior of the circuit arrangement when the frequency of the input signals E changes can be determined by the choice of the charging and discharging currents and the capacitance of the capacitor C1.
  • a further resistor R6 fulfills the function of the current source ST3 and the capacitor C2 acts as an integrating element 12.
  • the switch S is an inverter G, which is connected to the inverting output of the flip-flop F and is designed as an integrated component and, as already mentioned, likewise has no collector resistor and which discharges the capacitor C2 and keeps it in the discharged state as long as the square-wave signal R has the binary value 0.
  • the described embodiment illustrates one possibility of square wave signals with a circuit arrangement generation, which is largely composed of digital components, but also of analog components. If the repetition frequency of the input signals E permits, the circuit arrangement can, however, also be constructed exclusively from digital components.
  • the integrators I1 and I2 are each formed from a counter that is advanced by a correspondingly high-frequency clock.
  • the threshold value SW corresponds to a predetermined counter reading.
  • the comparator K then corresponds to a digital comparator which constantly compares the counter reading given by the counter with the given counter reading.
  • the switch S corresponds to an input of the counter, with which the counter is reset to its initial value.
  • a circuit arrangement designed in this way has the advantage that it can be produced entirely as an integrated circuit and can be adapted to different conditions by simply changing the counting clock frequency.

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  • Manipulation Of Pulses (AREA)
EP84109510A 1983-08-12 1984-08-09 Montage pour la génération de signaux rectangulaires Expired EP0135121B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT84109510T ATE26370T1 (de) 1983-08-12 1984-08-09 Schaltungsanordnung zum erzeugen von rechtecksignalen.

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE3329269 1983-08-12
DE19833329269 DE3329269A1 (de) 1983-08-12 1983-08-12 Schaltungsanordnung zum erzeugen von rechtecksignalen
US63675284A 1984-08-01 1984-08-01
US06/935,080 US4736118A (en) 1983-08-12 1986-11-24 Circuit arrangement to generate squarewave signals with constant duty cycle

Publications (2)

Publication Number Publication Date
EP0135121A1 true EP0135121A1 (fr) 1985-03-27
EP0135121B1 EP0135121B1 (fr) 1987-04-01

Family

ID=27191202

Family Applications (1)

Application Number Title Priority Date Filing Date
EP84109510A Expired EP0135121B1 (fr) 1983-08-12 1984-08-09 Montage pour la génération de signaux rectangulaires

Country Status (3)

Country Link
US (1) US4736118A (fr)
EP (1) EP0135121B1 (fr)
DE (1) DE3329269A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015028186A1 (fr) * 2013-08-30 2015-03-05 Robert Bosch Gmbh Circuit et procédé de génération d'un signal de sortie à rapport cyclique variable
EP3864744A4 (fr) * 2018-10-09 2022-07-20 Aistorm Inc. Matrice commutée à base de charge et procédé associé

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5028888A (en) * 1989-11-15 1991-07-02 Level One Communication, Inc. Multistage current-controlled oscillator
US5841306A (en) * 1992-08-18 1998-11-24 Samsung Electronics Co., Ltd. Pulse generator for generating output pulse of a predetermined width
US5451893A (en) * 1994-05-13 1995-09-19 Samsung Semiconductor, Inc. Programmable duty cycle converter
JP3460913B2 (ja) * 1995-09-29 2003-10-27 旭化成マイクロシステム株式会社 可変遅延時間発生回路とその方法
US6563655B1 (en) * 1996-05-20 2003-05-13 Texas Instruments Incorporated Method and apparatus for failsafing and extending range for write precompensation
TW358283B (en) * 1996-06-26 1999-05-11 Oki Electric Ind Co Ltd Remote testing device
US6154076A (en) * 1997-09-19 2000-11-28 Texas Instruments Incorporated Phase alignment circuit for periodic signals
JP3567747B2 (ja) * 1998-07-31 2004-09-22 富士通株式会社 電圧制御発振器及び周波数−電圧変換器
US6121805A (en) * 1998-10-08 2000-09-19 Exar Corporation Universal duty cycle adjustment circuit
JP3790076B2 (ja) * 1999-11-15 2006-06-28 株式会社東芝 アナログ同期回路
US6320438B1 (en) 2000-08-17 2001-11-20 Pericom Semiconductor Corp. Duty-cycle correction driver with dual-filter feedback loop
KR100381020B1 (ko) * 2001-06-30 2003-04-23 주식회사 하이닉스반도체 일정 듀티사이클을 갖는 구형파 펄스 발생기
US6518809B1 (en) 2001-08-01 2003-02-11 Cypress Semiconductor Corp. Clock circuit with self correcting duty cycle
CN1874152B (zh) * 2005-05-30 2010-04-28 厦门优迅高速芯片有限公司 3v-5v自校正占空比时钟芯片输出电路
US7705685B2 (en) * 2007-12-06 2010-04-27 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Low-voltage oscillator with capacitor-ratio selectable duty cycle
US8884676B2 (en) * 2011-08-23 2014-11-11 National Semiconductor Corporation Clock generator with duty cycle control and method
CN103138718B (zh) * 2011-11-24 2016-08-31 中国北车股份有限公司 信号处理装置、处理方法和电力机车
CN103187951B (zh) * 2011-12-31 2016-09-07 意法半导体研发(深圳)有限公司 用于生成斜坡信号的全集成电路
US8754690B2 (en) * 2012-10-26 2014-06-17 International Business Machines Corporation Programmable duty cycle setter employing time to voltage domain referenced pulse creation
CN103856186B (zh) * 2012-12-05 2016-12-21 戴泺格集成电路（天津）有限公司 占空比调节电路和调节方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2019685A (en) * 1978-04-21 1979-10-31 Amp Inc Electric circuit arrangement
FR2425178A1 (fr) * 1978-05-02 1979-11-30 Motorola Automobile Generateur de signal pour un dispositif d'allumage electronique

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US3753012A (en) * 1972-02-17 1973-08-14 Motorola Inc Circuit for providing precise time delay
FR2241162B1 (fr) * 1973-08-16 1976-09-17 Cit Alcatel
US3883756A (en) * 1973-12-27 1975-05-13 Burroughs Corp Pulse generator with automatic timing adjustment for constant duty cycle
US4276860A (en) * 1979-11-01 1981-07-07 Motorola, Inc. Apparatus for the generation of monostable pulses having predetermined durations independent of input signal period
US4404481A (en) * 1980-10-20 1983-09-13 Matsushita Electric Industrial Co., Ltd. Capacitance to voltage conversion apparatus
US4532442A (en) * 1981-10-23 1985-07-30 Black Ian A Noise reduction in electronic measuring circuits
JPS5916470A (ja) * 1982-07-20 1984-01-27 Sony Corp パルス検出回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2019685A (en) * 1978-04-21 1979-10-31 Amp Inc Electric circuit arrangement
FR2425178A1 (fr) * 1978-05-02 1979-11-30 Motorola Automobile Generateur de signal pour un dispositif d'allumage electronique

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015028186A1 (fr) * 2013-08-30 2015-03-05 Robert Bosch Gmbh Circuit et procédé de génération d'un signal de sortie à rapport cyclique variable
US9705480B2 (en) 2013-08-30 2017-07-11 Robert Bosch Gmbh Circuit and method for generating an output signal having a variable pulse duty factor
EP3864744A4 (fr) * 2018-10-09 2022-07-20 Aistorm Inc. Matrice commutée à base de charge et procédé associé

Also Published As

Publication number Publication date
EP0135121B1 (fr) 1987-04-01
DE3329269A1 (de) 1985-02-28
US4736118A (en) 1988-04-05

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