EP0092211B2 - Elektronisches Zeitprogramm-Schaltgerät - Google Patents

Elektronisches Zeitprogramm-Schaltgerät Download PDF

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Publication number
EP0092211B2
EP0092211B2 EP83103713A EP83103713A EP0092211B2 EP 0092211 B2 EP0092211 B2 EP 0092211B2 EP 83103713 A EP83103713 A EP 83103713A EP 83103713 A EP83103713 A EP 83103713A EP 0092211 B2 EP0092211 B2 EP 0092211B2
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EP
European Patent Office
Prior art keywords
switching
time
data
store
switching device
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Expired - Lifetime
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EP83103713A
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German (de)
English (en)
French (fr)
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EP0092211A1 (de
EP0092211B1 (de
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Winfried Brandenberg
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Legrand GmbH
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Legrand GmbH
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Priority to AT83103713T priority Critical patent/ATE30974T1/de
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G15/00—Time-pieces comprising means to be operated at preselected times or after preselected time intervals
    • G04G15/006—Time-pieces comprising means to be operated at preselected times or after preselected time intervals for operating at a number of different times

Definitions

  • the present invention relates to an electronic time program switching device according to the preamble of claim 1.
  • time program switching device previously mainly time switches with electromechanical drive and mechanical switching devices, such as radially displaceable switching segments, pluggable switching fingers or the like, have recently become increasingly high. So now and in the future there will probably be more demands that at least several time switch programs, i.e. with differences in different days of the week and also for several switching channels with partially different time switching programs should be as easy and error-free to set.
  • the switching data record cannot be entered and displayed completely, but only a partial section thereof, e.g. with a single day of the week, either an ON switching time or an OFF switching time; Combinations e.g. of several days of the week with the same ON and OFF switching times are neither possible in the display nor can they be checked at the same time.
  • a pattern for a programming sheet is therefore included in the operating instructions.
  • the invention is therefore based on the object of improving a time or time program switching device according to the preamble of claim 1 and its assemblies, i.e. the display device for the ON and OFF switching days with any number of days of the week and possibly different switching channels - optionally adjustable in any change of the sections of the complete data set - combined with the operating elements and intermediate memories in such a way that they can be controlled and designed so that the individual switching times and additional data can be configured can be entered in any order and inputs of inadmissible switching time data are excluded from the outset, incorrect or no longer required input data of switching times can be corrected in individual sections and complete data sets with ON and OFF switching times, weekday (s) and secondary data, as desired, for example selected switching channels or choice between ON or OFF switching time, can be clearly read and adjusted or corrected during the entire setting process.
  • Fig. 1a the top view - from the front as a front view - is shown on the timer with closed housing 1, from which one can see the division of the front panel 2 into the control panel 3 and the display panel 4.
  • the control panel 3 itself is divided into subfields 5 to 8 according to the order of the controls, the bottom 5 being the function selection main switch 9 «STEL / AUT and the group of switching channel selection switches 10 to 13 ( « S1 to S4 »), the upper strip 14 of the keypad 6 «SET the function selection button 15 (CLOCK), 16 (ON switching time) and 17 (OFF switching time), the middle strip 18 and the lower strip 19 the setting button « h »20 (hours), «M» 21 (minutes), «s» 22 (seconds), «d1-7» (weekdays), «S1-4» 24 (switching channels) and «Q» 25 (acknowledgment) are assigned, the last-mentioned button belongs to the variant of the single-digit entry possible in the two cases «d1-7» and «S1-4», in
  • the complete data record for a switching time pair - in the case of a query - or a part of it when entering for the first time after complete deletion - is displayed, with the switching time image in an upper half 30 for the ON switching time with a first symbol "I” 31 and a lower half 32, mirrored from top to bottom, is divided with a second symbol "O" 33 and each half except the times "h", "m” and “s” with a colon between the dates for "h »And« m » below or above the same bar code 35, 36 in seven adjacent positions corresponding to the days of the week and in the right part 37 of the display field 4 arrows one above the other, for example 38 for the display of the selected switching channels.
  • the special division of the operating (3) and display fields (4) gives the user a particularly easy and fail-safe setting of the timer data.
  • the "UHR" function selection button he can set the built-in electronic clock by pressing the setting buttons 20 to 22 "h”, “m” and “s”, as well as "d1-7" for the day of the week that applies or press (for automatic pulse sequence) until the relevant section value matches the current time, whereupon he actuates the function selection button 29 "AUT" to transfer the set half data record to the intermediate memory 301 for the current time and release the continuation of the automatic operation of the electronic time program switching device and thus also the ongoing automatic adjustment release of the built-in electronic clock
  • the user For the purpose of setting the ON and OFF switching times, the user has only one of the function selection buttons «1» 16 and «O» 17 and then again in sequence - in any order - the setting buttons 20 to 25 for the associated switching times, days of the week and To actuate switching channels, also as long or as often until the desired values are displayed in the individual sections of the data record memory, if this is the case, he only has to press the function selection button 29 «AUT» or «PROGR, after which the im Display field 4, complete data record reproduced as associated digits, identifiers and symbols, is transferred into the main memory (418) or its associated register and the «AUT» mode is also restored.
  • the condition must be met that all sections of the complete data set, possibly also e.g. are entered as "zero" (00) - without actuating the button 20 to 25 belonging to a section, there is no display at all - i.e. that the record is "complete".
  • this condition can also be limited to a “half data record, in which case such a data is displayed alternately for the current time, for ON switching time and for OFF switching time - in a less simplified version, however, the completeness condition is checked for the entire data set.
  • the geometric arrangement of the setting buttons 20 to 25 and the function selection buttons 15 to 17 and 29 also makes operation easier, because the function selection buttons 15 to 17 and 29 in a common line 39, the group of buttons 26 to 28 for the query, correction and deletion in sections, which also includes the total reset by means of the pushbutton 41 «Reset, in a line 40 at right angles to it and the actual actuating buttons are accommodated in the sub-field in between.
  • Fig. 1 b a partial section in the longitudinal direction, the arrangement of the printed circuit board 51 is supported on both sides by self-aligning, by means of clamping fastening between ribs 52, which are integrally formed on the side wall 53 of the upper housing part, and the end faces of the side wall 54 of the lower housing part .
  • the function selection and the setting buttons 55 to 58 are each from one neck, e.g. 53, of rectangular cross-section and a head plate 60 composed of a rubber-like material made conductive with additives and in its entirety by an elastic support surface 61 and integrally and integrally connected to this.
  • the necks 55 to 59 are formed by the webs, which are integrally formed underneath the front plate 2, e.g. 62, 63, and the support surface 61 through the intermediate webs also integrally molded there, e.g. 64 held at a precisely uniform distance from the front plate 2 self-adjusting.
  • the semiconductor compact module 67 with the display device and associated electronic assemblies is installed directly under the window 68 in the front panel 2 in the display panel 66 and is electrically connected to the conductor tracks of the printed circuit board 51 by the associated connecting lugs.
  • On the inside of the printed circuit board 51 are printed circuit boards 69, 70 at right angles to it, as indicated, for mechanical stiffening and for mounting larger components, such as capacitors of the power supply part, a battery for the power reserve, and the relays.
  • Fig. 1c is the top view of the bare upper housing part 1 with holes 81, 82 for screwing it to the lower housing part, with openings for the window 83 belonging to the display device, for function selection and setting buttons, e.g. 84, 85, 86, function selector switch, e.g. 87, 88, and the masks 89, 90, 91 for the subfields 7, 7, 8 (in FIG. 1a).
  • buttons e.g. 84, 85, 86
  • function selector switch e.g. 87, 88
  • the masks 89, 90, 91 for the subfields 7, 7, 8 (in FIG. 1a).
  • Fig. 2a shows the bottom view of the upper housing part 101, the integrally formed frame 102 of the window 103 for the display device, not shown, and the holding frame 104 for this, as well as the openings, for example 105, for the necks not shown here, for example 106 of the fingers 107 belonging to a setting button (in FIG. 2c) and the guide ribs, for example 110 to 113, integrally formed on the underside of the front plate 109, which are combined to form a latticework 108, on all four sides of the rectangular openings, for example 105, and with one another and with this integrally molded stiffening ribs, for example 114, 115.
  • FIGS. 2a, b, c and d. 2e shows the top view of the completely unpopulated front plate 109 with the openings, for example 105 for a button neck, for example 106 and for a channel switch 121, as well as for the function selector main switch 122 ( «STEUAUT»).
  • FIG. 3 shows a longitudinal section A-B, supplemented by a longitudinal section through the lower housing part 151 and a phantom longitudinal view of the cover housing 152, through the upper housing part, which is equipped with a compact semiconductor module 153 for the display device and a group 154 of setting buttons.
  • relays 159 to 162 electrolytic capacitors 163, 164 and the other parts of the circuit board are arranged on the circuit boards 158, 159 attached at right angles to the underside of the circuit board on the longitudinal edges of the circuit board 155 Power supply part 165.
  • the phantom view also shows how the pot-shaped cover housing 152 is attached with the aid of clamping claws in the grooves with internal teeth 166, being put over the lower housing part.
  • FIG. 4a shows a variant of the front view with a different housing shape, in which the display 181 and control panels 182 are arranged one above the other with abutting longitudinal edges (to be understood only conceptually).
  • the explanations for Fig. 1a apply with regard to facilitating operation due to the geometric assignment of display field areas and switches or buttons according to their ranking, especially the increase in the displayed values per button or by pressing for a long time by a sequence, and for the days of the week and the channels of the ongoing forwarding each time the button is pressed and transferred to the programming memory only after the acknowledgment button is pressed, in the same way, so that further explanations are unnecessary.
  • the electronic equipment and consequently the equipment of the front panel - apart from the local arrangement - corresponds to that of FIG. 1 a.
  • FIG. 4b The front view for an exemplary embodiment electronically disassembled in relation to FIG. 1a or FIG. 4a is shown in FIG. 4b.
  • the numbers of the display 184, 185 of the ON switching time and corresponding to the OFF switching time indicate the hours or minutes, while the colons 186 arranged between them indicate the seconds or other sections of the minutes.
  • the bars 187, 188 above and below the number line «1 ... 7» show the weekday selected by button «d1-7» (189) and permanently saved by pressing the acknowledgment button «Q» (190) , then the subsequent bar flashes when the «d1-7» button is pressed and jumps one step at a time until the day in question is saved and acknowledged by the «Q» (190) button and is indicated by constant lighting.
  • the symbols «S», «L», «1» and «2» (191) belong to the switching channels, the symbols «I» and «O» (192, 193) show the selected partial data set for setting the ON and / or of the OFF switching times.
  • the «Check» button (194) the saved switching times are queried, with the «Clear» button (195) the polled switching times are deleted, by pressing the «Program» button (196) the (complete) data set is displayed in accordance with the switching time diagram in Display in memory; the button ("Clock picture") (197) is used to set the time that is constantly running in the background, the button “I / O” (198) to choose between "ON and” OFF "switching times and to start operation the time switch for setting and automatic operation, switches 199 and 200 of the operating or channel switching optionally to «Set / Program» or «Automatic independent of this».
  • the parts with a dashed line are missing in the single-channel version of the time program switching device.
  • the printed circuit board 215 together with its side printed circuit boards 216, 217 is between the upper housing part 201 and the lower housing part 203 using the ribs, e.g. 206 and 210 clamped in place and in shape.
  • One side circuit board has a connector plug 219 on the part protruding from the floor.
  • the lower housing part (151 in Fig. 3) is shown with a bottom view, a longitudinal section EF and a top view in Fig. 6a, b and c.
  • the height-offset form which on the one hand offers a larger space for the power supply in the room part 221, while the elongated room part 222 offers space for connection plug strips, means for connecting the installation and the lower room part 225 is sufficient for the larger components, such as electrolytic capacitors, batteries and relays, on the other hand the printed circuit board with the connector strip extends through the slot 223 in the intermediate floor 224.
  • the grooves 226, 227 with offset toothed inner surfaces 228 and the integrally molded sleeves 229, 230 for screwing to the upper housing part are arranged on the side walls.
  • the spacer rods 231, 232 for the self-adjustment of the distance and the position of the cover housing are also integrally formed on the underside of the intermediate floor 224.
  • Fig. 7a for a longitudinal section AB
  • Fig. 7c a cross section IK
  • Fig. 7d for a cross section GH
  • Fig. 7e for a longitudinal section CD through the lower housing part
  • Fig. 7b for a side view in the direction of arrow N
  • Fig. 7f for a side view in the direction of arrow O on the lower housing part
  • FIG. 8 and 9 show the cover housing (202 in FIG. 5b) in cross sections JK (FIG. 8a), LO (FIG. 8c), in longitudinal section A-H (FIG. 8b), in a top view of the interior (FIG. 8d), repeatedly shown in bottom view (Fig. 9a) and front view (Fig. 9b).
  • the screw sleeves (214 in Fig. 5b) are designated with 241, 242, on the side walls are integrally molded ribs, e.g. 243, 244, for supporting the side walls of the lower housing part (FIGS. 6 and 7) on its lugs (233, 234) attached to the upper edge.
  • Break-out opening areas 247 and 248, 249, 250 are provided in the floor 245 and in the front wall 246 for connecting lines and assembly.
  • Other integral parts are e.g. the fitting parts 251 for the lower housing part.
  • 10 shows a greatly simplified block diagram with the most important electronic assemblies. It can be used to store the intermediate memory 301 for the sections 302 to 305 of the current time, which are connected as consecutive counters with the levels 60 (s), 60 (m), 24 (h) and 7 (d), both when the Set the drawn position of the switches 306 from the buffer 307 with a data record read in there to the current time, and also continuously feed the electronic clock module (buffer 301) from the frequency divider pulse source controlled by an oscillator 308, as well as the sections of the buffer Load 307 in sections from the data record memory 310, its sections being set by means of clock pulses from the clock generator 309 by actuating the setting button switch 311 and with changeover switches 311a set to ON or OFF switching times by means of clock pulses.
  • the electronic clock module buffer 301
  • the frequency divider pulse source controlled by an oscillator 308
  • the sections of the buffer Load 307 in sections from the data record memory 310 its sections being set by means of clock pulses from the
  • the buffer memory 307 can be connected to the input memory 312 of a display device and to the main memory 313 via the line group 314.
  • a complete data record is shoveled from the working memory 313 into the intermediate memory 307, while the current time is displayed by the display device.
  • the latter and one of the two half-data sets for ON and OFF switching times are located in sections at the inputs of the arithmetic-logic comparator units 314a, which, in the case of equality, have a signal at their outputs via the AND logic elements 315, which are controlled (not shown in detail) the sections switch the switching devices together with the signal of the channel selection section 316 to ON and OFF operating states.
  • Fig. 11 shows a schematic overview of the division of the overall block diagram with logical logic levels - here as AND or. OR gate for parallel data processing and the unity of the block diagrams 11a to 11d.
  • the area code and 325 (AUT) for taking over the automatic operation of the electronic time switch are located on one side at the clock pulse source T 1 , T 2 - which is still to be explained - and are on the output side via the AND gates with the complementary outputs Q of the FLIP-FLOP - Links 331 to 335 of the other function selection buttons linked.
  • the FLIP-FLOP element (eg 332) controlled by pressing a button (eg 322) has the Q output and the inputs of all other FLIP-FLOP elements 331, 333, 334 and 335 through the non-enabled AND- Links 326, 328, 329 and 330 locks.
  • H signals are present on the output lines 336 (UHR), 337 (AUT), 338 ( «I») and 339 ( «O») and 340 (AS1 7) as long as no other function selection key than that of the set FLIP-FLOP element has been actuated.
  • the function selection main switch «AUTISTEL 341 is located at some point in the circuit, whereby the same output effect as with the « AUT »function selection button 325 is achieved - but blocked.
  • the switching channel setting switches 342 serve to block the control circuit of the switching devices in one of the operating states: remain ON, OFF or INACTIVE, in which they remain set.
  • the set outputs of the monostable FLOP elements 332 (ON) or (ON) and 333 (OFF) or (AUT) (Fig. 11a) are as indicated by circles, e.g. 374, indicated, linked by NAND (or NEG) elements 375, 376 to the output signals of the FLIP-FLOP elements 368 to 372, so that they indicate via FLIP-FLOP elements 379, 380 output signals whether all of the relevant push buttons 351 to 355 are actuated; only then is an H signal given both for the "ON" actuation routine and for the "OFF” one and passed on via the AND gate 377 on line 378 for a positive result of the completeness check.
  • These output signals also control, via the OR gate 381, a time-delayed, monostable FLOP gate whose complementary Q output signal 382 is on the reset line 383 for the reset inputs.
  • the «ABF» key 356 therefore only reloads a data record stored in the working memory into the input memory 312 of the display device and thus interrupts the «AUT» routine if the «AS1 ...» function selection key has been pressed beforehand, i.e. A signal is present on line 384 and enables the forwarding of the “ABF” signal to line 366 via AND gate 385.
  • the actual record signals go from the relevant output of one of the AND gates 360 to 364 to the individually assigned buffer memories 387 to 391 of the data record memory 392 and set them to their corresponding values depending on the number of clock pulses entered; the buffer memory sections 387 and 391 are designed as sliding memories, so that after each input which is to be stored, this is entered into the actual register 387 'by a signal at the output of the AND gate 366 belonging to the acknowledgment actuating key «QUI» 357. or 391 '- if necessary in addition to the positions already occupied - must be stored.
  • the data contents of the sections "Switching time” and “Switching channel” are taken from the outputs 393 and 394 of the data record memory 392.
  • FIG. 11c shows, the function selection signals "I”, “O”, “AS1 ..”, 401 to 403 "AUT” 404 and the actuating signal ABF »386, with the outputs « SZ »(switching times) 405 and "SK” (switching channels) 406 and OFF switching time 409, 410 of auxiliary register 412 for the complete data set, and switching channel 411, as well as input 413 of the electronic clock module and input 414, as well as outputs 415 (ON switching time), 416 (OFF switching time) and 417 (switching channel) of the working memory 418 through a chain 419 of AND gates and the AND gate 429 in the latter together with the completeness signal on line 421 (378 in Fig. 11 b) logically combined .
  • the data transports in connection with the working memory 418 are controlled by the central unit 422 including decoders in connection with a program memory 423 and possibly with an external additional read / write memory 424.
  • 11d shows the assemblies of the electronic watch assembly 441 with the time segment stages 442 (day of the week “d”), 443 (hours “h”), 444 (minutes “m”) and 445 (seconds “s”) »)
  • the clock generator 446 consisting of an oscillator 447 and various divider stages, including for 1 ms-1/2 s, 1/8 s and 1 s clock signal outputs, e.g. T 1 and T 2 , and (1 s) for the ongoing advancement of the electronic clock assembly 441.
  • the time segment stages 442 to 445 can also be set from the data record memory (392 in FIG. 11b) via the line 448 and the AND gate 449 when the function signal “UHR” 336 is present on the line 450.
  • FIG. 12 shows an example with logical serial logic stages for the comparison of data record sections using shift registers when processing the time comparison of time and programmed ON or OFF switching time.
  • the associated data and half data sets are in registers 471 and 472 for the days of the week, 473 and 474 for «h», «m» and «s» for the current time and the stored switching time, and registers 475 and 476 for the switching channels of an intermediate memory 478 loaded from the main memory 477 via the lines 479, 480 and 481.
  • the registers 472, 473 of the switching times have shift registers 482 to 485 and 486, 487 on the input side and output side and the registers for the switching channels only on the output side arranges.
  • the shift registers each switch the input and / or the output of the relevant time segment register to the next one.
  • the clock pulses are released by means of multiple links using AND gates between clock signal line 488 via a first AND gate 489 with the AND gates controlled by CARRY and STATUS output signals of comparator stage 490 with a 491 negated on one side and a 492 negated on both sides. If the comparator element 490 determines equality at the next clock pulse and the CARRY and STATUS outputs are high, the AND element 493 is released and a clock pulse is transmitted to the further shift registers 484, 485 and via the counter 494 and the AND element 495 487 is given, so that the comparison for the next section is released.
  • the individual data record sections are not queried in parallel, but in series
  • the section from a principle block diagram of FIG. 13 operates according to the same principle as in FIG. 12 for an example of the evaluation of the position key codes.
  • the constants corresponding to the key codes are stored in register 501, for the subordinate area, namely «QUI» (3), «CLE» (4), «S1-4» (5), «TAG» (6) , «SEK» (7), «ABF» (6), «STU» (9) and «MIN» (A), in register 502 for an «ABF» subroutine for the «QUI» key, which in turn controls the Constants corresponding to key codes for “TAG” (6) and “S1 ..
  • ALE arithmetic-logic unit
  • buffer group 552 input and output register R 553, output register D 554, working memory 555 including programming memory, Buffer for complete data records, program memory 556 including program counter, return address memory and table memory, operation part decoder 557 and display device including auxiliary modules and clock 558 are integrated.
  • Read lines 559 and address lines 560, 561 of the function selection switches, keys and setting keys combined to form a matrix 563 are connected to the input and output register in such a way that the switch and key codes are constants from the codes of the lines - Divisions can be divided, e.g.
  • the output signal of the logic combination or comparator stage 551 controls the relays 562 via intermediate modules 561 and further logic elements.
  • the operating parts of the command words of the program memory are processed in accordance with the steps of the command counter, as it corresponds exactly to the serial logical combination of the exemplary embodiments of FIGS. 12 and 13 which operates purely in hardware.
  • Fig. 16 shows that the display, change and deletion of the data of the displayed, set days of the week and switching channels takes place in the same simple manner.
  • the days of the week for the ON switching time are in the upper line and for the OFF switching time in the lower line - Consistent with the image 605 on the display, a series of bars that may light up next to each other are shown, with «flashing hatched and « constant » ie are drawn in solid black.
  • Fig. 16a at 1) the sequence of the bar images according to the actuation of the button «d1-7», if necessary or partially several times, «Q» acknowledgment and at 2) the switching time data record corresponding to the setting of the days of the week.
  • Excerpt reproduced. 16b shows how the setting according to 1) is extended by pressing the "d1-7" button, again in some cases several times without acknowledgment, and the "Q" button to add Tuesday and Wednesday to the additional days of the week Thursday and Saturday , 3).
  • Fig. 16c top 1)
  • the absence of a setting of ON switching days is indicated, which is eliminated by pressing the «d1-7» key twice according to 2) and pressing the «Q» key.
  • Fig. 16d line 1)
  • the blinking of all bars shows that no day of the week has been set at all, which is why according to 2) the button "I / O" sets it to ON, i.e. «I» - and actuation of the buttons «d1-7 and « Q and then 3) reset of the button «I / O» - setting to OFF, i.e. «O» - and also pressing buttons «d1-7» and «Q the data record section for the days of the week must be corrected.
  • 16e is just as easy to correct - here more ON switching days than OFF switching days in line 1) - by preselecting the OFF switching times «O» using the «I / O» key and pressing the «d1» key 7 »and « Q »for setting the weekdays Monday, Tuesday, Wednesday and Friday and acknowledging them for storage.
  • Fig. 16f 1 line 1) indicates an incomplete entry of the switching channels (only «SL 1 »), which are supplemented by pressing the «S1-2» and «Q» buttons to that in line 2), as is the consequence of Button images can be recognized.
  • pressing the «S1-2» button switches to the first switching channel, the symbol flashing, after which pressing the «Q» button can save this correction .
  • FIG. 17 shows a block diagram for an example of the compatibility check (plausibility) of the individual data of the complete switching times data record found by the completeness check in the permanently formatted data record memory 621 with the partial areas for the symbol “I” 622, the days of the week “ d »623, the switching time of day in hours « h » minutes » m »and seconds « s »624, of the ON switching time partial data record, as well as the symbol « O »625, the days of the week « d »626, the switching -Daytime 627 of the OFF switching time partial data record, with the switching channel or switching channels «SK» 628 associated entered data for possible interpretation (s).
  • index "I” means belonging to the switch-on times, index “O” to the switch-off times, index P to the programming memory and index A to the working memory, "T” means switching time of day) must be compared and related to each other put :
  • the requirements regarding the switching channels Kp and K A are determined by the comparator stage 644, for the number of days of the week d A / I or d A / I / AZ + 1 (in the intermediate memories 645 and 646) and the number of days of the week d P / o or dA / o (buffer 635, 647), and d p / 1 , or d A / I in the comparator stages 648, 649, the data of the symbols O / P , and O / A in the subareas 625 , 650 and finally the data of the symbols I / P and I A or I / A / / AZ + 1 (the latter in the partial areas 651, 652) checked or compared in the comparator stages 653, 654; the result signals of these comparator stages must be H without exception, so that the AND gate 655 also provides an H signal at its output, which is present at the second input of the AND gate 643 and at the first input of the AND gate 643
  • the actual plausibility check consists of the further linking steps: First, at the inputs of the comparator stage 656 via shift registers 636 and 657, the selected data of the most significant digits of the ON-switching times of the day T p / I of the programming memory are stored in the intermediate registers 638 and 658 621 or T A / I of the working memory 418, ie of the register 630 - that is to say of the addressed switching time data record; At the inputs of comparator stage 659, shift registers 637 and 660 are the data selected and stored in the intermediate registers 639 and 661 of the most significant digits of the OFF switching times of the day Tp / o of the data record memory 621 and T A / o of the register 630 of the working memory 418.
  • the outputs of the comparator stages 656, 659 and 662 are connected by the OR gate 665, the AND gate 666 and partly by the AND gate 643a, the output signal of which increases the address counter 629 by one, and finally the AND gate 667 is linked in such a way that that on output line 668 - if conditions are met - an enable signal for the transfer of the complete switching time data record in data record memory 621 to the addressed subarea between AZ and AZ + 1 of working memory 418 occurs via line 669 and AND elements 670, 671; the AND gate 671 also becomes conductive only when the inputs of the completeness check are present at its inputs 672, 673 (outputs of the AND gates 375, 376 in FIG. 11b).

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)
  • Programmable Controllers (AREA)
  • Electronic Switches (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)
EP83103713A 1982-04-20 1983-04-17 Elektronisches Zeitprogramm-Schaltgerät Expired - Lifetime EP0092211B2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT83103713T ATE30974T1 (de) 1982-04-20 1983-04-17 Elektronisches zeitprogramm-schaltgeraet.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3214372A DE3214372A1 (de) 1982-04-20 1982-04-20 Elektronisches zeitschaltgeraet
DE3214372 1982-04-20

Publications (3)

Publication Number Publication Date
EP0092211A1 EP0092211A1 (de) 1983-10-26
EP0092211B1 EP0092211B1 (de) 1987-11-19
EP0092211B2 true EP0092211B2 (de) 1991-07-03

Family

ID=6161256

Family Applications (1)

Application Number Title Priority Date Filing Date
EP83103713A Expired - Lifetime EP0092211B2 (de) 1982-04-20 1983-04-17 Elektronisches Zeitprogramm-Schaltgerät

Country Status (8)

Country Link
US (1) US4594007A (enrdf_load_stackoverflow)
EP (1) EP0092211B2 (enrdf_load_stackoverflow)
AT (1) ATE30974T1 (enrdf_load_stackoverflow)
DE (2) DE3214372A1 (enrdf_load_stackoverflow)
ES (1) ES521646A0 (enrdf_load_stackoverflow)
GR (1) GR78191B (enrdf_load_stackoverflow)
IE (1) IE54902B1 (enrdf_load_stackoverflow)
WO (1) WO1983003688A1 (enrdf_load_stackoverflow)

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Publication number Priority date Publication date Assignee Title
DK163842C (da) * 1984-11-27 1992-08-24 Knudsen Nordisk Elect Programmerbart elektrisk ur
JPS61275691A (ja) * 1985-05-31 1986-12-05 Casio Comput Co Ltd アラ−ム時計
DE3622681A1 (de) * 1986-07-05 1988-01-21 Diehl Gmbh & Co Elektronische uhr mit einer digitalanzeige
JP2526938B2 (ja) * 1987-11-16 1996-08-21 オムロン株式会社 プログラマブル・タイムスイツチ
DE8816400U1 (de) * 1988-04-25 1989-06-15 Siemens AG, 1000 Berlin und 8000 München Zeitschaltgerät mit einer mikrocomputergesteuerten Programm-Einstellvorrichtung
DE4008940A1 (de) * 1990-03-20 1991-09-26 Elero Antrieb Sonnenschutz Elektronische rolladensteuerung
ATE153123T1 (de) * 1991-02-04 1997-05-15 Vaillant Gmbh Eingabeeinrichtung für einen programmierbaren heizungsregler
FR2775865B1 (fr) * 1998-03-04 2000-06-09 Valeo Electronique Tableau de commande a circuit imprime, en particulier pour vehicule automobile
US6060980A (en) * 1999-08-20 2000-05-09 Bedol; Mark A. Appointment timer
US20050083786A1 (en) * 2003-10-15 2005-04-21 Shih-Cheng Tsai Multi-functional timer
WO2006052079A2 (en) * 2004-11-10 2006-05-18 Lg Electronics Inc. Remote monitor in electric home appliances

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CH15464A (de) * 1897-11-12 1898-06-15 Wangelin Friedr Allseitig geschlossener Schwimmkörper
GB923609A (en) * 1959-07-17 1963-04-18 Pye Ltd Automatic control arrangement
JPS5726468B2 (enrdf_load_stackoverflow) * 1974-04-19 1982-06-04
GB1523128A (en) * 1974-12-27 1978-08-31 Kienzle Uhrenfabriken Gmbh Electronic digital clocks
JPS536075A (en) * 1976-07-06 1978-01-20 Citizen Watch Co Ltd Multi-function watch
DE2643250B2 (de) * 1976-09-25 1978-07-27 Braun Ag, 6000 Frankfurt Zentralgesteuerte Uhr
US4158432A (en) * 1976-12-10 1979-06-19 Texas Instruments Incorporated Control of self-test feature for appliances or electronic equipment operated by microprocessor
JPS53113581A (en) * 1977-03-15 1978-10-04 Citizen Watch Co Ltd Portable electronic device with watch function
JPS54101206A (en) * 1978-01-26 1979-08-09 Nissan Motor Channel selection programming device for radio receiver
US4279012A (en) * 1978-10-23 1981-07-14 Massachusetts Microcomputers, Inc. Programmable appliance controller
US4204196A (en) * 1978-11-17 1980-05-20 Sveda Michael P Modular electronic timer
US4293915A (en) * 1979-04-16 1981-10-06 Pacific Technology, Inc. Programmable electronic real-time load controller
US4264034A (en) * 1979-08-16 1981-04-28 Hyltin Tom M Digital thermostat
US4393915A (en) * 1980-03-24 1983-07-19 Olson Carl G Web securing device
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US4418333A (en) * 1981-06-08 1983-11-29 Pittway Corporation Appliance control system

Also Published As

Publication number Publication date
GR78191B (enrdf_load_stackoverflow) 1984-09-26
EP0092211A1 (de) 1983-10-26
IE54902B1 (en) 1990-03-14
DE3374613D1 (en) 1987-12-23
EP0092211B1 (de) 1987-11-19
ATE30974T1 (de) 1987-12-15
DE3214372C2 (enrdf_load_stackoverflow) 1988-07-14
ES8402083A1 (es) 1984-01-16
DE3214372A1 (de) 1983-11-03
ES521646A0 (es) 1984-01-16
US4594007A (en) 1986-06-10
WO1983003688A1 (en) 1983-10-27
IE830891L (en) 1983-10-20

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