EP0080043A2 - Méthode pour l'enregistrement de données dans une mémoire de rafraîchissement d'image d'un dispositif d'affichage - Google Patents

Méthode pour l'enregistrement de données dans une mémoire de rafraîchissement d'image d'un dispositif d'affichage Download PDF

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Publication number
EP0080043A2
EP0080043A2 EP82108854A EP82108854A EP0080043A2 EP 0080043 A2 EP0080043 A2 EP 0080043A2 EP 82108854 A EP82108854 A EP 82108854A EP 82108854 A EP82108854 A EP 82108854A EP 0080043 A2 EP0080043 A2 EP 0080043A2
Authority
EP
European Patent Office
Prior art keywords
control unit
line
image
memory
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP82108854A
Other languages
German (de)
English (en)
Other versions
EP0080043B1 (fr
EP0080043A3 (en
Inventor
Pedro Trambale
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to AT82108854T priority Critical patent/ATE31370T1/de
Publication of EP0080043A2 publication Critical patent/EP0080043A2/fr
Publication of EP0080043A3 publication Critical patent/EP0080043A3/de
Application granted granted Critical
Publication of EP0080043B1 publication Critical patent/EP0080043B1/fr
Expired legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G09G1/16—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible the pattern of rectangular co-ordinates extending over the whole area of the screen, i.e. television type raster
    • G09G1/165—Details of a display terminal using a CRT, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory

Definitions

  • the invention relates to a method for writing data under the control of a memory access controller into a frame buffer of a data display device, which has an electron beam tube and an image control unit with at least two line buffers designed as a clock interface.
  • the display In the case of a data display device which has an electron beam tube, the display needs to be refreshed at approximately 50 Hz, for example, for a flicker-free display.
  • the data to be displayed must be stored in a buffer, from which they are called up again and again in the rhythm of the image repetition. This buffer is called a frame buffer.
  • the image repetition memory must, on the one hand, be available to the display device for the refresh process, but it must also be able to record external data, for example from a data memory, if the image is to be changed on the screen. If the refreshing process is not to be interrupted when a picture is changed, the writing in of new data must be interleaved with the readout of the locations for the picture refreshing.
  • the interleaving can take place, for example, in such a way that the image repetition memory during a beam is read out while the image repetition memory is being overwritten during the beam return.
  • the beam return time is shorter than the beam lead time.
  • the sum of all beam travel times during an image cycle is therefore substantially smaller than the sum of all beam return times.
  • the available beam return times during an image cycle may not be sufficient to overwrite a memory area or to overwrite the entire memory area.
  • the overwriting must therefore take place in several image cycles. A new picture can only be built up slowly. In addition to the loss of time, the slow image build-up can be disruptive for an operator.
  • Insert page 2a It was therefore the object of the invention to specify a method of the type mentioned above with which the image repetition memory is overwritten within one image cycle. thereby
  • the image control unit sends a request signal to the memory access control at the beginning of all line runs, and then a signal for writing data to the image repetition memory and one of the line buffers is given, that data is simultaneously stored in the image repetition memory during the line run and one of the line buffers are written in, and that the image control unit emits a synchronization signal at the end of an image cycle, which ends the writing of the data.
  • visual display device in which the characters to be displayed are stored in coded form in a frame buffer serving as background memory.
  • the characters are fed to an image control unit via two buffer memories designed as a clock interface.
  • One of the buffer memories can be connected to the background memory and the other to the image control unit.
  • the image control unit controls the two buffer memories in such a way that the other buffer memory is loaded from the background memory with the characters to be shown below, simultaneously with the display of the contents of one buffer memory on the screen.
  • the data word to be written into the image repetition memory is thus simultaneously written into one of the line buffers. Since the writing process takes place while the beam is moving in, the beam return times are available for further writing processes. For example, further control data can be read in. A larger number of control functions can thus be carried out on the data display device. The ease of use and the area of application of the data display device are increased. Further developments of the invention result from the subclaims.
  • the data display device shown in FIG. 1 contains a display device 8 for displaying characters.
  • the display unit 8 is provided with a cathode ray tube with a screen, and with deflection amplifiers and a circuit part which modulates the intensity of the electron beam on the screen.
  • the visual display device contains an image control unit 6 and an image and character generator 7 for generating the character shapes and for formatting the image on the screen.
  • a data memory with random access serves as a refresh memory 3.
  • An input / output interface 13 is provided for the output of external data, for example from a computer. Data can be entered from a keyboard 5 via a keyboard interface 4.
  • the data display device has a function control unit 1 and a system memory 22 with random access.
  • Data for controlling the function control unit 1 are stored in a program memory 2.
  • the function control unit 1 can be designed, for example, as a microprocessor.
  • a first memory access controller is not shown, with which a direct memory access to the system memory 22 is controlled. becomes.
  • a system clock determines the speed of data transfer during memory access.
  • Data lines which are designated as data bus 9, are provided for the transmission of data.
  • the individual units are addressed via address lines, which are referred to as address bus 10.
  • Data bus 9 and address bus 10 can each have 16 lines, for example.
  • the control of the units; for example to select the "write” or "read” function, is carried out via control lines 11.
  • the data, address and control lines can be used for bidirectional transmission. They are each connected to the function control unit 1, the program memory 2, the system memory 22, the image repetition memory 3, the input / output interface 13, the keyboard interface 4, the image control unit 6 and the character generator 7 and the first memory access control.
  • the image control unit 6 is connected to the character generator 7 via video address lines 12. This is connected to the display unit 8 via a video data line 23. In addition, the image control unit 6 is connected to the display unit 8 via two synchronization lines 14. The data transmission from the image control unit 6 to the character generator 7 takes place at a rate determined by the display unit 8.
  • the data on an electron beam tube only remains visible on the screen for a limited time, it must be refreshed at regular intervals. All data to be displayed are stored in the refresh memory 3. If the display on the screen is not to be changed, the image repetition memory 3, the image control unit 6 and the character generator 7 can be decoupled from the function control unit 1 via switches 16, 17 in the data and address bus 9, 10. The refreshing process then takes place under the control of the image control unit 6.
  • the screen is written, for example, in n lines, the image repetition memory being read out once.
  • the characters to be displayed are written on the screen.
  • the beam retrace time 41 the electron beam jumps back without writing, for example to a new beginning of the line or from the last line to the beginning of the image.
  • the sum of all beam return times 41 of an image cycle is considerably shorter than the sum of the beam return times 40, so that those during an image cycle available frame return times are not sufficient to overwrite the entire frame buffer.
  • the 3 shows the frame buffer 3, the image control unit 6 with a first and second line buffers 24, 25 and a second ⁇ memory access controller 18 for the frame buffer 3 .
  • the data bus 9 is connected via a controllable switch 16 to the frame buffer 3 and the first line buffer 24 .
  • the address bus 10 is connected to the image repetition memory 3 and the image control unit 6 via a controllable changeover switch 17.
  • the toggle switch 17 connects address lines 10 ′ leading from the image repetition memory 3 to the image control unit 6 alternatively to the address bus 10 or to address lines 10 ′′, which lead to the second memory access control 18.
  • the address bus 10 is also connected to an address decoder 15.
  • the control lines 11 are divided into a first, second and third control line 11 ', 11'',11'''.
  • the first control line 11 ' is connected to the address decoder 15.
  • the second control line 11 ′′ is connected to a switching mechanism 20.
  • the circuit arrangement shown in FIG. 2 operates in three different operating modes A, B, C.
  • the function control unit 1 controls all the operations required for starting up the visual display device. This includes, for example, loading parameters for the display format into the image control unit 6.
  • the switch 16 is closed.
  • the address lines 10 ' are connected to the address bus 10 via the changeover switch 17, that is to say the second memory access control 18 is decoupled from the image repetition memory 6.
  • the screen control unit 6 controls the reading of the image repetition memory, the second memory access control 18 outputting the required addresses on the address lines 10 '.
  • the switch 16 is open and the address lines 10 ′′ are connected to the address lines 10 ′ via the changeover switch 17.
  • the image repetition memory 3 is overwritten with external data under the control of the first memory access control.
  • the word to be written into the frame buffer 3 is written into the line buffer 24.
  • the switch 16 is closed and the changeover switch 17 connects the address lines 10 'to the data bus 10.
  • the two line buffers 24, 25 serve as a clock interface.
  • the system clock is written into the line buffer 24.
  • the line buffer 25 is read out at the clock of the display unit 8 via the video data lines 12. It is essential that the overwriting of the image repetition memory 3 takes place during the line traversal of the electron beam.
  • the three operating modes A, B, C are determined by three states of the switching mechanism 20.
  • the switching mechanism 20 is controlled via three outputs of the decoder, which are numbered from 1 to 3. It is synchronized with the system clock and a synchronization clock of the display unit 8 via the lines 29 and 30.
  • the output signals of the switching mechanism 20 are changed in the case of a system cycle and / or a synchronization cycle.
  • the switching mechanism 20 has three flip-flops (FF) 26, 27, 28.
  • the switching mechanism 20 consists of four OR gates 34, 35, 36, 37 and two AND gates 31, 33.
  • the image repetition memory 3 has an input RD which effects the reading in of the data present on the data bus 9 as soon as a signal is applied. It also has an input WR, which causes data to be output on data bus 9 as soon as a signal is present.
  • the image control unit 6 also has an input WR. A signal at this input causes data from data bus 9 to be transferred to line buffer 24.
  • the second memory access controller 18 has an output RD and an output WR. A signal at one of these outputs has the effect that when the memory is accessed directly on the image repetition memory 3, ie when an image is refreshed in the display unit 8, the image repetition memory 3 is read or written.
  • Each signal on one of the lines described can assume one of two levels 1 or 0.
  • the writing in the frame buffer 3 and the line buffer 24 takes place when on WR Input is at an O level.
  • the image repetition memory 3 is read out when an O level is present at the RD input. is present.
  • Switch 16 is closed when a 0 level is present at its control input, and is open at a 1 level.
  • the switch 17 connects the address lines 10 'to the address bus 10 at a 0 level, and connects the address lines 10' to the address lines 10 '' at a 1 level.
  • the outputs 1, 2, 3 of the address decoder 15 have the levels 0.0.1, 0.1.0 and 1.0.0 in the operating states A, B, C.
  • the switching mechanism 20 has the following states:
  • the AND gate 31 switches through a memory access request signal coming from the image control unit 6 to the first memory access control unit.
  • the OR gate 35 and the AND gate 33 connect a write signal from the control line 11 ′′ to the image repetition memory 3 and to the image control unit 6.
  • the OR gates 36, 37 each block a write or write message coming from the second memory access controller 18. Read signal.
  • the address decoder 15 is activated by the function control unit 1 via the line 11 '.
  • a data word on address bus 10 is then decoded. This data word determines the output levels of the address decoder 15.
  • the output levels of the address decoder 15 are taken over by the FF26 and FF 27.
  • the output levels of the FF26 are switched on via FF28. There is therefore a 1 level at the AND gate 31.
  • a line start signal on line 39 is switched through. The line start signal occurs at the beginning of the. Line scrolling of a picture cycle.
  • the first memory access controller then outputs the first memory address of the image repetition memory on the address bus 10.
  • the data word present on the data bus 9 is written into the first memory location and into the first line buffer 24 while reading out from the second line buffer 25.
  • the next line start signal is written into the next memory locations of the frame buffer 3, while the first line buffer 24 is overwritten after its contents have been reloaded into the second line buffer.
  • the entire picture repetition memory 3 is thus overwritten.
  • the image control unit 6 then generates a synchronizing signal which clocks the FF28, so that new levels are present at its outputs.
  • the switching mechanism 20 has two FF 26, 27, which are clocked with the system clock via a line 29.
  • a third flip-flop 28 is clocked via line 30, which is connected to image control unit 6 and memory access control 18 and on which the synchronization clock is applied.
  • the synchronization clock consists of a signal that is generated after each image cycle.
  • the first output of the address decoder 15 is connected to the S output of the FF 26.
  • One of the two other outputs of the address decoder 15 is connected to an input of the FF 27.
  • the output of FF 26 is connected to the S input of FF 28 and the complementary output of FF 26 is connected to the R input of FF 28.
  • the non-inverting output of FF 28 is fed back to the R input of FF 26.
  • the inverting output of the FF 27 is connected to the OR gate 34 and an AND gate 32.
  • a line 39 leads from the image control unit 6 to the AND gate 31 and to the memory access control 18, on which a signal is output when a line of an image cycle is displayed (line start signal). It means that an access to the refresh memory 3 or the system memory 22 is desired (memory access request signal).
  • the inputs of the AND gate 32 are connected to the outputs 32 of the FF 27 and 28.
  • the output of the AND gate 32 is connected to the switch 16, the changeover switch 17 and the inverter 38.
  • the output of inverter 38 is connected to OR gates 36 and 37.
  • the RD Output of the memory access control 18 is connected to the OR gate 37.
  • the WR Output of the memory access control 18 is connected to the OR gate 36.
  • the output of the OR gate 36 is connected to the RD input of the frame buffer 3.
  • the output of the OR gate 37 is connected to the AND Member 33 connected.
  • the output of the AND gate 3-3 is connected to the WR input of the image control unit 6.
  • the negating output of the FF 28 is connected to the OR gate 35.
  • the negating output of the FF 27 is connected to the OR gate 34.
  • the outputs of the OR gates 34, 35 become the AND gate 33 connected.
  • the control line 11 ′′ is connected to the OR gates 34, 35.
  • the non-inverting output of the FF 28 and the line 29 are connected to the AND gate 31. Its output is connected to the input of the first memory access control.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Dram (AREA)
EP82108854A 1981-09-30 1982-09-24 Méthode pour l'enregistrement de données dans une mémoire de rafraîchissement d'image d'un dispositif d'affichage Expired EP0080043B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT82108854T ATE31370T1 (de) 1981-09-30 1982-09-24 Verfahren zum einschreiben von daten in einen bildwiederholspeicher eines datensichtgeraetes.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3138930 1981-09-30
DE3138930A DE3138930C2 (de) 1981-09-30 1981-09-30 Datensichtgerät

Publications (3)

Publication Number Publication Date
EP0080043A2 true EP0080043A2 (fr) 1983-06-01
EP0080043A3 EP0080043A3 (en) 1985-07-03
EP0080043B1 EP0080043B1 (fr) 1987-12-09

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EP82108854A Expired EP0080043B1 (fr) 1981-09-30 1982-09-24 Méthode pour l'enregistrement de données dans une mémoire de rafraîchissement d'image d'un dispositif d'affichage

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Country Link
US (1) US4970501A (fr)
EP (1) EP0080043B1 (fr)
AT (1) ATE31370T1 (fr)
DE (1) DE3138930C2 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0132562A2 (fr) * 1983-07-18 1985-02-13 International Business Machines Corporation Système d'affichage d'images composites
EP0148659A2 (fr) * 1983-11-25 1985-07-17 Sony Corporation Circuit de commande d'affichage vidéo
EP0482678A2 (fr) * 1984-07-23 1992-04-29 Texas Instruments Incorporated Contrôleur de système vidéo avec un circuit de dépassement de l'adresse de ligne
FR2669448A1 (fr) * 1990-11-19 1992-05-22 Bull Sa Architecture de terminal et circuit de gestion.

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3319944A1 (de) * 1983-06-01 1984-12-06 Siemens AG, 1000 Berlin und 8000 München Einrichtung zum schreib-lese-betrieb eines bildspeichers
DE3838827A1 (de) * 1988-11-17 1990-05-23 Thomson Brandt Gmbh Bildwiedergabesystem
JPH03116194A (ja) * 1989-09-29 1991-05-17 Mitsubishi Electric Corp ディスブレイ制御装置
FR2664999B1 (fr) * 1990-07-23 1992-09-18 Bull Sa Dispositif d'entree sortie donnees pour l'affichage d'informations et procede mis en óoeuvre par un tel dispositif.
WO1993020513A1 (fr) * 1992-04-07 1993-10-14 Chips And Technologies, Inc. Procede et appareil permettant un marquage de defilement offrant une largeur de bande accrue aux systemes de donnees repetitives dynamiques a memoire
US20020140818A1 (en) * 2001-04-02 2002-10-03 Pelco System and method for generating raster video test patterns

Citations (2)

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Publication number Priority date Publication date Assignee Title
US4156904A (en) * 1976-08-25 1979-05-29 Hitachi, Ltd. Computer systems having a common memory shared between a central processor and a CRT display
DE3026225A1 (de) * 1980-07-10 1982-02-04 Siemens AG, 1000 Berlin und 8000 München Datensichtgeraet

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US4117469A (en) * 1976-12-20 1978-09-26 Levine Michael R Computer assisted display processor having memory sharing by the computer and the processor
US4177462A (en) * 1976-12-30 1979-12-04 Umtech, Inc. Computer control of television receiver display
US4146877A (en) * 1977-05-26 1979-03-27 Zimmer Edward F Character generator for video display

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
US4156904A (en) * 1976-08-25 1979-05-29 Hitachi, Ltd. Computer systems having a common memory shared between a central processor and a CRT display
DE3026225A1 (de) * 1980-07-10 1982-02-04 Siemens AG, 1000 Berlin und 8000 München Datensichtgeraet

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
ELECTRONIC DESIGN, Band 28, Nr.17, August 1980, Seiten 123-127, ROCHELLE PARK, (US). R. DAVIES: "Refresh graphics peripheral configures to the host system".* Figur 1 ; Seite 123 - Seite 124, Zeile 6 * *
ELECTRONIC DESIGN, Band 29, Nr. 9, April 1981, Seiten 131-138, WASECA, MN, (US). T. ROSSL: "Low-cost CRT control does more with less" * Figuren 1-3, 5 ; Seiten 133-134 * *
ELECTRONICS, Band 52, Nr. 14, Juli 1979, Seiten 136-139, NEW YORK, (US). L. TROTTIER et al.: "Transparent memory ends conflicts over CRT control" * Seite 139 ; Figuren 1-4 * *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0132562A2 (fr) * 1983-07-18 1985-02-13 International Business Machines Corporation Système d'affichage d'images composites
EP0132562A3 (en) * 1983-07-18 1989-07-26 International Business Machines Corporation Composite display system
EP0148659A2 (fr) * 1983-11-25 1985-07-17 Sony Corporation Circuit de commande d'affichage vidéo
EP0148659A3 (fr) * 1983-11-25 1989-10-25 Sony Corporation Circuit de commande d'affichage vidéo
EP0482678A2 (fr) * 1984-07-23 1992-04-29 Texas Instruments Incorporated Contrôleur de système vidéo avec un circuit de dépassement de l'adresse de ligne
EP0482678A3 (en) * 1984-07-23 1992-09-16 Texas Instruments Incorporated Video system controller with a row address override circuit
FR2669448A1 (fr) * 1990-11-19 1992-05-22 Bull Sa Architecture de terminal et circuit de gestion.
EP0487400A1 (fr) * 1990-11-19 1992-05-27 Bull S.A. Architecture de terminal et circuit de gestion
US5799202A (en) * 1990-11-19 1998-08-25 Rongione; Eric Video terminal architecture without dedicated memory

Also Published As

Publication number Publication date
US4970501A (en) 1990-11-13
EP0080043B1 (fr) 1987-12-09
DE3138930A1 (de) 1983-04-14
ATE31370T1 (de) 1987-12-15
EP0080043A3 (en) 1985-07-03
DE3138930C2 (de) 1985-11-07

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