EP0018409A1 - Verfahren zum herstellen von halbleiterbauelementen - Google Patents

Verfahren zum herstellen von halbleiterbauelementen

Info

Publication number
EP0018409A1
EP0018409A1 EP19790901088 EP79901088A EP0018409A1 EP 0018409 A1 EP0018409 A1 EP 0018409A1 EP 19790901088 EP19790901088 EP 19790901088 EP 79901088 A EP79901088 A EP 79901088A EP 0018409 A1 EP0018409 A1 EP 0018409A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor body
conductivity
electrical properties
dopant
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19790901088
Other languages
German (de)
English (en)
French (fr)
Inventor
Hanno Schaumburg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV, Koninklijke Philips Electronics NV filed Critical Philips Gloeilampenfabrieken NV
Publication of EP0018409A1 publication Critical patent/EP0018409A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/005Control means for lapping machines or devices
    • B24B37/013Devices or means for detecting lapping completion
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • G01R31/265Contactless testing
    • G01R31/2656Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement

Definitions

  • the invention relates to a method for producing semiconductor components with at least one surface zone of a specific conductivity type produced by introducing a dopant into a semiconductor body.
  • predetermined critical sheet resistances with close tolerance had been set by several successive thermal treatments of the semiconductor body, the sheet resistance being measured after the individual treatment steps.
  • the invention has for its object to design the method according to the preamble of claim 1 so that it is easily possible to control the thermal treatment of a semiconductor body so that a predetermined dopant distribution or conductivity is reliably maintained.
  • This object is achieved in that the electrical properties of a test figure formed in part of the surface of the semiconductor body are measured and at the same time the surface of the semiconductor body is subjected to a thermal treatment which changes the dopant distribution or the conductivity by means of intense optical radiation directed at it , which is canceled as soon as the measured electrical properties have reached a predetermined value.
  • the single figure shows a disk-shaped semiconductor body 1 which, in addition to the (four only schematically indicated) semiconductor components to be produced.
  • 2 carries a test figure 3.
  • the sheet resistance can be measured with the aid of contact tips 4 placed on the contact areas of this test figure.
  • the wafer After the dopant has been introduced into the wafer 1 by ion implantation, the wafer is. so intensely optically irradiated that the implanted layer heals. This irradiation is preferably carried out with the aid of a continuously or pulsed laser.
  • the decrease in sheet resistance that occurs during this thermal treatment is measured in situ via test figure 3 and contact tips 4. After reaching the predetermined target value for the sheet resistance, the optical radiation is switched off and the thermal treatment is abruptly stopped.
  • the thermal treatment can be carried out by irradiation with a laser, but also by irradiation from strong other light sources, scanned or unscanned.
  • the method according to the invention can be used with particular success for the precise manufacture of sheet resistors, in particular high-resistance resistors in integrated circuits.
  • Another preferred application of the method according to the invention is the reproducible setting of predetermined small base widths in bipolar high-frequency transistors.
  • test figure used to measure the dopant distribution or conductivity in the semiconductor body need not be exclusively a zone or arrangement of zones used for this purpose, but also by one or a part of one of the ones to be produced Semiconductor components can be formed.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Computer Hardware Design (AREA)
  • Toxicology (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Mechanical Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Bipolar Transistors (AREA)
EP19790901088 1978-08-30 1980-03-25 Verfahren zum herstellen von halbleiterbauelementen Withdrawn EP0018409A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2837749 1978-08-30
DE19782837749 DE2837749A1 (de) 1978-08-30 1978-08-30 Verfahren zum herstellen von halbleiterbauelementen

Publications (1)

Publication Number Publication Date
EP0018409A1 true EP0018409A1 (de) 1980-11-12

Family

ID=6048210

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19790901088 Withdrawn EP0018409A1 (de) 1978-08-30 1980-03-25 Verfahren zum herstellen von halbleiterbauelementen

Country Status (5)

Country Link
EP (1) EP0018409A1 (ja)
JP (1) JPS55500701A (ja)
DE (1) DE2837749A1 (ja)
GB (1) GB2042262A (ja)
WO (1) WO1980000522A1 (ja)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4350537A (en) * 1979-10-17 1982-09-21 Itt Industries Inc. Semiconductor annealing by pulsed heating
US4380864A (en) * 1981-07-27 1983-04-26 The United States Of America As Represented By The Secretary Of The Air Force Method for providing in-situ non-destructive monitoring of semiconductors during laser annealing process
DE3905569A1 (de) * 1989-02-23 1990-08-30 Wolfgang Kuebler Messleiter
DE19800196C2 (de) * 1998-01-07 1999-10-28 Guenter Nimtz Verfahren zur Herstellung von Flächenwiderstandsschichten
KR100390908B1 (ko) * 2001-04-30 2003-07-10 주식회사 하이닉스반도체 선택적 에피택셜 성장 공정 평가용 마스크

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3461547A (en) * 1965-07-13 1969-08-19 United Aircraft Corp Process for making and testing semiconductive devices
GB1246386A (en) * 1968-02-08 1971-09-15 Ibm Improvements relating to diffusion of material into a substrate

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8000522A1 *

Also Published As

Publication number Publication date
GB2042262A (en) 1980-09-17
WO1980000522A1 (en) 1980-03-20
JPS55500701A (ja) 1980-09-25
DE2837749A1 (de) 1980-03-13

Similar Documents

Publication Publication Date Title
DE2631873C2 (de) Verfahren zur Herstellung eines Halbleiterbauelements mit einem Schottky-Kontakt auf einem zu einem anderen Bereich justierten Gatebereich und mit kleinem Serienwiderstand
DE102008062494B4 (de) Vorrichtung zur Erwärmung von Substraten sowie Verfahren zur Erwärmung von Substraten
EP0048288B1 (de) Verfahren zur Dotierung von Halbleiterbauelementen mittels Ionenimplantation
DE3136105A1 (de) "verfahren und vorrichtung zum tempern von halbleitern"
DE2812740A1 (de) Verfahren zum herstellen einer vertikalen, bipolaren integrierten schaltung
DE1246890B (de) Diffusionsverfahren zum Herstellen eines Halbleiterbauelements
EP0343369A1 (de) Verfahren zum Herstellen eines Thyristors
DE1544275C3 (de) Verfahren zur Ausbildung von Zonen unterschiedlicher Leitfähigkeit in Halbleiterkristallen durch Ionenimplantation
DE2160427B2 (de) Verfahren zur Herstellung eines Halbleiterwiderstandes mit implantierten Ionen eines neutralen Dotierungsstoffes
DE1544211A1 (de) Verfahren zum Herstellen von Halbleitervorrichtungen
DE3637006A1 (de) Siliziumeinkristallsubstrat mit hoher sauerstoffkonzentration sowie verfahren und vorrichtung zu seiner herstellung
DE2425185A1 (de) Verfahren zum herstellen einer halbleitervorrichtung
DE1514807A1 (de) Verfahren zur Herstellung von Halbleitervorrichtungen
DE602004007756T2 (de) Ein Lichtbestrahlungsverfahren und ein Lichtbestrahlungsapparat
DE1514359B1 (de) Feldeffekt-Halbleiterbauelement und Verfahren zu seiner Herstellung
EP0018409A1 (de) Verfahren zum herstellen von halbleiterbauelementen
DE102004039208B4 (de) Verfahren zur Herstellung eines Leistungsbauelements mit einer vergrabenen n-dotierten Halbleiterzone und Leistungsbauelement
DE10056872C1 (de) Implantationsüberwachung unter Anwendung mehrerer Implantations- und Temperschritte
EP0062883A2 (de) Verfahren zur Herstellung eines integrierten bipolaren Planartransistors
DE3839210A1 (de) Verfahren zum axialen einstellen der traegerlebensdauer
EP0008043B1 (de) Integrierter bipolarer Halbleiterschaltkreis
DE3139712A1 (de) Glueheinrichtung
DE2301384A1 (de) Verfahren zur herstellung einer halbleiteranordnung und durch dieses verfahren hergestellte anordnung
EP0018556B1 (de) Anordnung und Verfahren zum selektiven, elektrochemischen Ätzen
DE2060348A1 (de) Verfahren zur Herstellung einer Halbleiteranordnung und durch dieses Verfahren hergetellte Halbleiteranordnung

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed
AK Designated contracting states

Designated state(s): FR

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: N.V. PHILIPS' GLOEILAMPENFABRIEKEN

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19820418

RIN1 Information on inventor provided before grant (corrected)

Inventor name: SCHAUMBURG, HANNO