EP0017245B1 - Circuit semiconducteur intégré monolithique comportant un registre à décalage commandé par impulsions d'horloge - Google Patents
Circuit semiconducteur intégré monolithique comportant un registre à décalage commandé par impulsions d'horloge Download PDFInfo
- Publication number
- EP0017245B1 EP0017245B1 EP80101822A EP80101822A EP0017245B1 EP 0017245 B1 EP0017245 B1 EP 0017245B1 EP 80101822 A EP80101822 A EP 80101822A EP 80101822 A EP80101822 A EP 80101822A EP 0017245 B1 EP0017245 B1 EP 0017245B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- gate
- output
- register
- shift register
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G10—MUSICAL INSTRUMENTS; ACOUSTICS
- G10H—ELECTROPHONIC MUSICAL INSTRUMENTS; INSTRUMENTS IN WHICH THE TONES ARE GENERATED BY ELECTROMECHANICAL MEANS OR ELECTRONIC GENERATORS, OR IN WHICH THE TONES ARE SYNTHESISED FROM A DATA STORE
- G10H1/00—Details of electrophonic musical instruments
- G10H1/36—Accompaniment arrangements
Definitions
- Such a semiconductor circuit is known from US-A-4142433.
- Such a semiconductor circuit can, for. B. for signal control of electronic devices, for. B. an electronic organ can be used with advantage. So z. B. in such organs, the signal to be evaluated in each case generated by pressing the keys in the manual and passed on from there for evaluation.
- the automatic generation of a melody accompaniment in an electronic organ requires an automatic recognition of the current state of the game, that is, the recognition of the digital signals generated by the manual. For musical reasons, it is desirable not to let certain playing states, i.e. certain combinations of pressed game keys, influence the generation of the accompaniment. Such a case is e.g. B. given the simultaneous actuation of keys, the associated tones are only apart by a semitone width.
- the invention is based on the object of specifying a circuit arrangement with which the respective game state is recognized and with which the undesired game states are rendered ineffective.
- FIGS. 1 to 4. 3 is a semiconductor circuit corresponding to the invention in the block diagram and in FIGS. 1 and 2 an embodiment of the item. 1 and 2 called ring shift registers and in FIG. 4 a system used for generating the signals required for the linkage or regeneration, respectively.
- the ring shift register shown in FIGS. 1 and 2 is discussed in more detail, although this does not always have to form part of the semiconductor circuit according to the invention. However, its importance is given for many cases, especially when the invention is used for musical purposes.
- the ring shift register RR shown in FIG. 1 consists of n register cells R; connected in series, the index i passing through the numbers 1, 2, ... n.
- the individual shift register cells R are designed as quasi-static register cells in the interest of simplifying the circuit, as can be seen from FIG. 2.
- the accruing, z. B. via the manual of the electronic organ supplied information arrives via the signal input E at - at the same time the feedback of the last register cell R n to the first register cell R 1 mediating OR gate OG to the one input of an AND gate UG, the output of which The first register cell R 1 is provided.
- the second input of the AND gate UG is controlled by the output of the second register cell R 2 .
- this output is connected to the second input of the AND gate UG via a negated AND gate (NAND gate) NG.
- This feedback of the output of a downstream register cell to the input of an upstream register cell has the effect that the input of the upstream register cell, i.e. in the example of register cell R 1 , only receives the signal ONE when the output of the downstream register cell, i.e. in the example of register cell R 2 , a NULL is pending.
- An auxiliary signal H applied to the second input of the NAND gate NG can also block the AND gate UG if necessary and thus the input of a signal present at the signal input E or via the feedback from the last register cell R n into the first register cell R.
- the described connection between the output of the register cell R 2 to the AND gate UG and the register cell R has the effect that, due to a ONE pending at the output of the register cell R 2, a pending at the output of the last register cell R n and via the OR Gate OG suppressed ONE to be forwarded, that is, it is eliminated from the information content circulating in the ring shift register RR, so that a correction of the circulating signal is possible in this way by eliminating an undesired ONE.
- Such a feedback can also be provided between other register cells R i if required be.
- FIG. 1 also shows a second possibility - to be used as an alternative to the correction option just described - of changing a signal circulating in the ring shift register RR.
- This is given by an AND gate U ', the output of which is at the reset input R' of the second register cell R 2 and one input of which is at the signal input of the first register cell Ri, while its second input is controlled by an auxiliary signal H if required.
- This AND gate U ' can only be caused to pass a one to the reset input R * of the register cell R 2 if there is a one at the input of the first register cell R 1 and a corresponding auxiliary signal H at the second input of the AND gate U * . If this is the case, then a ONE present in register cell R 2 is deleted.
- register cells R 1 , R 2 ,... R n are preferably used as register cells R 1 , R 2 ,... R n . These permit the design of the shift register cells R 1 and R 2 which can be seen in FIG. 2, which are then followed in a similar manner by the register cells R 3 , R 4 ,... R n . Initially, this is still the configuration of the ring shift register RR which is preferably to be used as a signal input and which may possibly be identical to the shift register SR which is used to apply the logic to be described below.
- the z. B. from the manual of the electronic organ forth signal input E of the ring shift register RR is in an embodiment according to FIG. 2 at an input of a NOR gate G 1 with three inputs, the second input of which is connected to the signal output of the last register cell R n and whose third input is at the output of an AND gate G 4 to be switched by an auxiliary signal H.
- the output of the first NOR gate (negated OR gate) G 1 leads via a transfer transistor T 1 to be controlled by the clock TM to an inverter G 2 and via this and via a second transfer transistor T 2 to the one input of a second NOR gate G 3 , the second transfer transistor T 2 being controlled by the clock TS. Furthermore, the input of the inverter G 2 is connected to the output of the second NOR gate G 3 via a third transfer transistor T 3 . A clock TSS is provided to control the third transfer transistor T 3 .
- the output of the second NOR gate G 3 forms the output of the first register cell R i . It is also connected to one input of the previously mentioned AND gate G 4 , the output of which leads back to the first NOR gate G 1 .
- one first has an input transfer transistor T 4 controlled by the clock TM and an AND gate G 6 provided with three inputs, which is connected with one of its inputs to the output of the first register cell R 1 .
- the source-drain path of the input transfer transistor T 4 leads on the one hand via the source-drain path of a further transfer transistor T 6 controlled by the clock TSS to the signal output of the second register cell R 2 , on the other hand via the series circuit of an inverter G 5 and a transfer transistor controlled by the clock TS T 5 to the one input of a NOR gate G 7 .
- This NOR gate G 7 has three inputs, one of which can be controlled via the inverter G 5 , the second through the output of the AND gate G 6 mentioned in the last paragraph and the third via a reset signal.
- This reset signal is also at the second input of the already mentioned output gate G 3 of the first register stage, which - in contrast to the gate G 7 - is only provided with two inputs.
- the configuration of the register cells R 3 to R n essentially corresponds to the two cells R 1 and R 2 . So they are also quasi-static register cells.
- the signal transferred from the respective upstream register cell via a transfer transistor controlled by the clock TM passes via an inverter and a further transfer transistor controlled by the clock TS to the input of a NOR gate, which at the same time forms the output of the cell in question.
- the output of the input transfer transistor of the relevant register cell Rj controlled by the clock TM is directly connected to the signal output of the NOR gate of the relevant cell.
- Another input of this NOR gate is used to apply reset pulses.
- an AND gate corresponding to the AND gate of register cell R 2 can be provided.
- a ring shift register RR shown in FIG. 2 is able, in a manner similar to an arrangement according to FIG. 1, to correct undesired dual combinations in the fed-in signal, such as those e.g. B. occur while pressing adjacent game buttons in the organ manual, and perform a clean signal of the actual system according to the invention.
- 12 tone names C, CIS, D, DIS, etc.
- the intervals between the tones are decisive.
- the digital signals generated via the manual are successful conditions via the input E into the ring shift register RR, the information already circulating in it being retained with the exception of the signal parts suppressed as a result of the corrective measures mentioned.
- the semiconductor circuit shown in FIG. 3 forms the core of the invention. This will now be described in more detail.
- a shift register SR which is preferably to be controlled by a ring shift register RR according to FIG. 2 or FIG. 1 in parallel operation or is identical to this, forms the input of the circuit shown in FIG. 3.
- This shift register SR like the shift register RR, must also be freed of information contained in it before start-up, which is brought about by a reset signal supplied by a common clock generator.
- a clock generator which is suitable for supplying the clock pulse sequences TM, TS and TSS, z. B.
- a clock according to the patent application P 2 845 379.4 (VPA 78 P 1 191; title: digital integrated semiconductor circuit) can be used.
- the course of the clocks TM, TS and TSS can also be found in this application.
- the cells of the shift register SR in FIG. 3 and the shift register SRG in FIG. 4 are expediently designed as quasi-static register cells. All these cells and also the further circuit parts provided in an arrangement according to the invention are expediently designed using MOS-IC technology.
- At least the output of two register cells S i of the shift register SR and in the preferred case the outputs of all register cells S; are connected to the logic L effecting a signal masking, while the individual register cells S i receive their information in parallel operation through the respectively assigned register cell R; of the ring shift register RR received.
- each of the outputs of the individual register cells is S; of the shift register SR each connected to an input of the logic L.
- the logic is composed in the usual way of elementary gates, in particular AND gates, OR gates, NAND gates, NOR gates, inverters or exclusive OR gates, in order to implement the desired logic function.
- the internal circuitry of the logic L is often designed such that a signal for fixing the counter reading of the dual counter Z only appears at the output of the logic for a certain signal present in the shift register SR.
- the outputs of the two last-mentioned AND gates A 1 and A 2 are each at one of the two inputs of an intermediate gate LA 1 , z. B. an OR gate, which forms a secondary output of the logic L, which is used to control an auxiliary system, for. B. the system shown in Fig. 4, is provided.
- the main output of the logic L is given in the example by an OR gate 0, the individual inputs of each of one of the intermediate gates LA; the logic L are controlled. This main output serves to fix the counter reading of a digital counter, ie pulse counter Z in the manner already defined above.
- the clock generator TG provided for clock control of the shift register SR serving to apply the logic L and possibly also the ring shift register RR outputs the clock pulses serving for the clock supply of the shift register SR at the same time to the counting input of a dual counter Z, the Q outputs of which in each case to the first input of an AND -Gatters A are placed, the other input of which is controlled by the main output of the logic L, that is to say by the output of the OR gate 0.
- OR gate 0 as the output of the logic L means that the counter reading of the dual counter Z is fixed each time, that is to say is passed on as a signal via the AND gate A when sent to ei nem the intermediate gate LA; a signal appears, which may be important for the further system for synchronization reasons.
- the configuration of the output of the logic L is provided by an AND gate or a NOR gate.
- a read-only memory ROM is provided, which is occupied in the respectively required manner, that is to say programmed, and is also designed as a matrix memory.
- Each column line S of this read-only memory ROM which is designed in a known manner, is connected to the signal output of one AND gate UN each.
- These AND gates UN are divided into groups G of the same size, each of which is one of the signal outputs of those already mentioned and through the intermediate gates LA; the logic L controlled first selection circuit AW 1 are assigned. For example, four such groups G are provided, each containing eight AND gates UN.
- the first selection circuit AW 1 is set by the logic L, as can be seen from FIG. 3.
- a further logic acted upon by the secondary outputs of the logic L can be provided in the selection circuit AW I , which ensures that a particular output of the selection circuit AW 1 receives the level ONE, while the other outputs maintain the level ZERO.
- the number of inputs of the selection circuit AW 1 controlled by the logic L that is to say via its secondary outputs and possibly also via its main output 0, matches the number of its outputs and thus the number of groups G, it is sufficient if everyone by the logic L controlled input of AW 1 controls an AND gate activated by a preselection, through the output of which a flip-flop, e.g. B. RS flip-flop. The nodes of the flip-flop not acted upon by the AND gate then each form an output of the selection AW 1 .
- the column powers of the read-only memory ROM are assigned to the individual register cells. If you give z. B. in the shift register SRG a signal consisting only of a ONE, it depends on the one hand on the position of the selection circuit and on the other hand by the number of shift cycles given after the introduction of the ONE on the shift register, which parts of the read-only memory ROM are activated.
- the output gates AG are given as OR gates, each of which has two inputs.
- the second selection circuit AW 2 can also by logic, for. B. the logic L can be controlled. If the circuit is used to design an electronic organ, however, a manually controlled selection circuit AW 2 will be preferred. she gets then a corresponding, e.g. B. Control task related to the rhythm of the game.
- the fundamental tone present in the signal present in the shift register SR is determined by the respectively fixed state of the dual counter Z, so that not only the key but also the associated fundamental tone is input into the signal required for controlling the signal generating system SG.
- This signal then has the task of generating the required accompaniment chord via a digitally controlled tone generator.
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Acoustics & Sound (AREA)
- Multimedia (AREA)
- Shift Register Type Memory (AREA)
- Logic Circuits (AREA)
- Electrophonic Musical Instruments (AREA)
Claims (21)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19792914518 DE2914518A1 (de) | 1979-04-10 | 1979-04-10 | Monolithisch integrierbare halbleiterschaltung |
DE2914518 | 1979-04-10 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0017245A2 EP0017245A2 (fr) | 1980-10-15 |
EP0017245A3 EP0017245A3 (en) | 1981-12-02 |
EP0017245B1 true EP0017245B1 (fr) | 1985-07-31 |
Family
ID=6067991
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP80101822A Expired EP0017245B1 (fr) | 1979-04-10 | 1980-04-03 | Circuit semiconducteur intégré monolithique comportant un registre à décalage commandé par impulsions d'horloge |
Country Status (4)
Country | Link |
---|---|
US (1) | US4403334A (fr) |
EP (1) | EP0017245B1 (fr) |
JP (1) | JPS55140900A (fr) |
DE (1) | DE2914518A1 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4402244A (en) * | 1980-06-11 | 1983-09-06 | Nippon Gakki Seizo Kabushiki Kaisha | Automatic performance device with tempo follow-up function |
US4612659A (en) * | 1984-07-11 | 1986-09-16 | At&T Bell Laboratories | CMOS dynamic circulating-one shift register |
JP2560317Y2 (ja) * | 1993-09-09 | 1998-01-21 | 大同ほくさん株式会社 | 浴 槽 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3530284A (en) * | 1968-03-25 | 1970-09-22 | Sperry Rand Corp | Shift counter having false mode suppression |
US3716725A (en) * | 1971-01-04 | 1973-02-13 | Chicago Musical Instr Co | Ring counter |
US3889568A (en) * | 1974-01-31 | 1975-06-17 | Pioneer Electric Corp | Automatic chord performance apparatus for a chord organ |
US4019417A (en) * | 1974-06-24 | 1977-04-26 | Warwick Electronics Inc. | Electrical musical instrument with chord generation |
DE2539950C3 (de) * | 1975-09-09 | 1981-12-17 | Philips Patentverwaltung Gmbh, 2000 Hamburg | Bassakkordautomatik |
JPS52137314A (en) * | 1976-05-13 | 1977-11-16 | Kawai Musical Instr Mfg Co Ltd | Code discriminator of automatic player |
JPS5333113A (en) * | 1976-09-09 | 1978-03-28 | Nippon Gakki Seizo Kk | Priority selector |
US4099048A (en) * | 1976-11-09 | 1978-07-04 | Westinghouse Electric Corp. | Count logic circuit |
US4300430A (en) * | 1977-06-08 | 1981-11-17 | Marmon Company | Chord recognition system for an electronic musical instrument |
US4282786A (en) * | 1979-09-14 | 1981-08-11 | Kawai Musical Instruments Mfg. Co., Ltd. | Automatic chord type and root note detector |
-
1979
- 1979-04-10 DE DE19792914518 patent/DE2914518A1/de not_active Withdrawn
-
1980
- 1980-04-03 EP EP80101822A patent/EP0017245B1/fr not_active Expired
- 1980-04-04 US US06/137,380 patent/US4403334A/en not_active Expired - Lifetime
- 1980-04-08 JP JP4613380A patent/JPS55140900A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
DE2914518A1 (de) | 1980-10-23 |
JPS55140900A (en) | 1980-11-04 |
EP0017245A2 (fr) | 1980-10-15 |
US4403334A (en) | 1983-09-06 |
EP0017245A3 (en) | 1981-12-02 |
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