Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
  • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
  • H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
  • H01L27/0788—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type comprising combinations of diodes or capacitors or resistors
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
  • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
  • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
  • G11C11/416—Read-write [R-W] circuits 

Definitions

• the invention relates to a highly integrated semiconductor arrangement containing a diode / resistor configuration according to the preamble of claim 1, which can preferably be used as a separating diode interacting with the selection lines of an integrated memory arrangement with a high-impedance leakage resistance.
• a constant endeavor in the development of integrated semiconductor circuit concepts consists in designing the individual or more circuit elements to be as space-saving as possible in order to be able to accommodate as many circuit elements or functions as possible on a semiconductor chip.
• Such increases in the degree of integration have a directly favorable effect on the costs, reliability, etc. of the products made from them.
• US Pat. No. 3,631,311 deals with an integrated semiconductor circuit arrangement which provides a transistor with a base leakage resistance integrated directly therewith. The resistance area extends on one side into the surrounding insulation area, whereby an external resistance connection can also be saved.
• the bleeder resistor integrated with the transistor base is designed as a so-called pinch or dumbbell resistor.
• Such a pinch resistor is a double-diffused resistor, in which the line channel of the actual resistance region is constricted in its cross section by introducing a further doping region of the opposite conductivity type. Relatively high-resistance values can be achieved in this way, without an otherwise inevitably high semiconductor area requirement when the sheet resistance is used.
• the invention solves the problem of specifying an integrated semiconductor arrangement for a diode / resistor configuration which is as space-saving as possible and which, in particular, requires as few external connection contacts and interconnection conductors as possible and can be produced by conventional process steps.
• the resistance should be able to be designed for high resistance values, as are required for leakage resistors and have the lowest possible parasitic capacitance.
• the invention provides for the extremely extensive integration of a Schottky diode with a pinch resistor connected to it, the pinch-up doping region of which also represents the cathode connection doping region of the Schottky-Doide.
• the Schottky contact can additionally be formed simultaneously with the resistance connection by a common metal electrode overlapping the associated P / N junction.
• the additional contact for the resistor can also be saved by extending the resistance area into the surrounding insulation area, via which the corresponding voltage supply then takes place when the resistor is used as a discharge resistor.
• the diode / resistor configuration constructed according to the measures of the invention is distinguished by an extremely small requirement for active semiconductor area, since it manages with a minimum of external connections and interconnections while avoiding intermediate insulation.
• the available high resistance value with only a small parasitic capacitive influence allows a versatile application, for. B. as a isolation diode / leakage resistance combination with low own power dissipation.
• the diode D is a Schottky diode with the anode connection A and the cathode connection K.
• the resistor R is connected to the anode A, and a reference voltage can be applied to the other connection VR. If the resistor R is used as a bleeder resistor, VR can, for example, be the most negative voltage occurring in the circuit.
• the symbol used for the resistor R in FIG. 1 is intended to indicate that this is a (known per se) pinch Resistance with a cut-off zone in the course of the resistance range.
• FIG. 2A now shows a particularly advantageous exemplary embodiment for the highly integrated embodiment of the circuit shown in FIG. 1 as a semiconductor arrangement.
• FIG. 2B additionally shows a cross-sectional illustration along the section line designated in FIG. 2A.
• the cross-sectional view in, Fig. 2B expanded in the sense of a perspective representation.
• the diode / resistor combination according to the invention can be produced by means of conventional methods which are customary in the field of integrated semiconductor circuits, which is why there is no need to go into this in the present context.
• a P-type semiconductor substrate 1, e.g. from single-crystal silicon.
• buried doping regions in the form of the known subcollector regions can be provided in the substrate 1, but are not shown in the present case for the sake of clarity.
• an epitaxial layer of the opposite conductivity type is usually applied to the substrate 1 using known epitaxial processes and is divided into individual, delimited regions 3 made of N-conducting semiconductor material by frame-shaped separation or isolation regions 2. These delimited regions 3 of the epitaxial layer serve in a known manner to accommodate the semiconductor components to be formed therein.
• such a delimited area 3 consists of N conductive semiconductor material the diode D and the resistor R integrated therewith arranged.
• the resistor R consists of the elongated P-conducting doping region 4, the cross-section of which is constricted in the manner customary for pinch resistors by introducing a further doping region 5 of the opposite conductivity type, in the present case made of N-conducting semiconductor material.
• the constriction doping region 5 has a smaller penetration depth than the resistance region 4.
• the pinch-off region 5 extends beyond the width of the resistance region 3 (at 6), so that there it is in connection with the semiconductor material surrounding the resistance region 4 in region 3 of the same conductivity type.
• the conventional doping methods such as diffusion or ion implantation, can be used to produce the doping regions 4 and 5.
• the resistance region 4 is equipped with a metal electrode, A, on a vein, in the exemplary embodiment of FIG. 2 at the right end.
• This metal electrode A forms an ohmic contact with the P-conducting resistance region 4. It is particularly advantageous in the context of the present invention to design the metal electrode A as an overlapping contact, so that it also extends beyond the resistance region 4 into the surrounding N conductive material of the epitaxial layer 3. As a result, in the present case, a rectifying Schottky-Coritakt is formed on the N-conducting semiconductor material of the layer 3 by the metal electrode A in addition to an ohmic contact of the resistance region 4.
• the metal electrode K can consist of the same metal as the metal electrode A, because the doping level of the pinch-up region 5 is higher than that of the semiconductor material in region 3, so that the matt electrode does not form an ohmic contact.
• the production of the metal electrodes A and K can also be carried out by means of conventional methods, e.g. B. by means of aluminum vapor deposition, sputtering, etc., take place.
• both the formation of the doping regions and the metallizations, together with the corresponding method steps can be carried out for the further circuit elements to be produced on the same semiconductor chip, z. B.
• the P conductive resistance region 4 can be made simultaneously with the base doping, the pinch-up doping region 5 with the emitter doping and the contacting with the other metallizations for the connections and conductor tracks on the chip.
• the circuit shown in FIG. 1 completes the diode D with its external connections A and K and the resistor R connected to the anode A.
• the resistor R as a bleed resistor for the most negative potential occurring in the circuit, the contact required on the resistance region 4 can finally be saved, according to an advantageous development of the invention, by having the resistance region 4 with its other end, in the exemplary embodiment shown on the left extends into the insulation zone 2 surrounding the semiconductor region 3. Since the insulation regions 2 for forming blocked P / N transitions are generally at the lowest potential occurring in the circuit, the resistor R receives the corresponding voltage supply at its connection for the reference potential VR without a special, area-consuming additional contact to have to provide.
• the diode / resistor combination shown in FIG. 1 is therefore extraordinarily high in terms of integration and only two external contacts realizable, which results in a considerable saving of space in comparison to a conventional design of such a circuit part, which is to be illustrated with the aid of FIG. 3 with the aid of a scale comparison of areas.
• FIG. 3 shows a conventional, integrated semiconductor arrangement for the circuit part shown in FIG. 1.
• Fig. 3 is in a first isolated semiconductor region 8 of the pinch resistor with its conductive resistance P, area 9 and formed the A bschnürdot ists Scheme 10 as well as the two outer terminals 11 and 12.
• the Schottky diode is made in a second semiconductor region 13 from N conductive semiconductor material.
• the metal electrode 14 forms the Schottky junction for the anode, while the further metal electrode 15 on the N-conducting doping region 16 forms an ohmic contact for the cathode of the Schottky diode.
• a comparison of the area of the conventional embodiment according to FIG. 3 with the embodiment according to a preferred embodiment of the invention according to FIG. 2A results in an area saving of approximately 54% if the diode / resistor configuration according to FIG. 1 is integrated according to the invention.
• FIG. 4 is as an application example of the use of the diode / resistor configuration according to the invention in the control area of a semiconductor memory.
• FIG. 4 shows a section of a memory arrangement which is limited to a bit line pair BLO, BL1.
• BLO bit line pair
• BL bit line pair
• Each such group of transistors belonging to a bit line pair or to a word line can be decoupled from the corresponding transistors of another bit line pair or another word line by means of the diode / resistor configuration shown in the boxed area 21 according to FIG. 1. If a chip selection signal is present, all decoupling diodes D on the chip in question are reverse-biased, so that write-in or read-out processes can be carried out for the memory cells on the chip.
• a bleeder resistor R is additionally provided parallel to the anode connection of the decoupling diode D. So that only the lowest possible current can flow through the bleeder resistor in the selection case, the bleeder resistor R should have the highest possible resistance value and the most parasitic capacitance. These properties go directly into the switching times that can be achieved and the power loss.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Semiconductor Integrated Circuits (AREA)
• Electrodes Of Semiconductors (AREA)
• Static Random-Access Memory (AREA)
• Bipolar Integrated Circuits (AREA)
• Semiconductor Memories (AREA)

Applications Claiming Priority (2)

Publications (2)

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Family Applications (1)

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Cited By (1)

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• 1977
  • 1977-07-26 DE DE19772733615 patent/DE2733615A1/de not_active Withdrawn
• 1978
  • 1978-03-23 US US05/889,169 patent/US4170017A/en not_active Expired - Lifetime
  • 1978-06-19 DE DE7878100195T patent/DE2860462D1/de not_active Expired
  • 1978-06-19 EP EP78100195A patent/EP0000472B1/fr not_active Expired
  • 1978-06-26 JP JP7662078A patent/JPS5424585A/ja active Granted

Non-Patent Citations (2)

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