EP0000472B1 - Dispositif semiconducteur à haute densité d'intégration comprenant une structure diode-résistance - Google Patents

Dispositif semiconducteur à haute densité d'intégration comprenant une structure diode-résistance Download PDF

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Publication number
EP0000472B1
EP0000472B1 EP78100195A EP78100195A EP0000472B1 EP 0000472 B1 EP0000472 B1 EP 0000472B1 EP 78100195 A EP78100195 A EP 78100195A EP 78100195 A EP78100195 A EP 78100195A EP 0000472 B1 EP0000472 B1 EP 0000472B1
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EP
European Patent Office
Prior art keywords
resistor
area
pinch
diode
doping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP78100195A
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German (de)
English (en)
Other versions
EP0000472A1 (fr
Inventor
Wilfried Klein
Erich Dipl.-Ing. Klink
Volker Dipl.-Phys. Rudolph
Friedrich Dipl.-Ing. Wernicke
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International Business Machines Corp
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International Business Machines Corp
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Publication date
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Publication of EP0000472A1 publication Critical patent/EP0000472A1/fr
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
    • H01L27/0788—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type comprising combinations of diodes or capacitors or resistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 

Definitions

  • the invention relates to a highly integrated semiconductor arrangement containing a diode / resistor configuration according to the preamble of claim 1, which can preferably be used as a separating diode interacting with the selection lines of an integrated memory arrangement with a high-impedance leakage resistance.
  • a constant endeavor in the development of integrated semiconductor circuit concepts is to design the individual or more circuit elements to be as space-saving as possible in order to be able to accommodate as many circuit elements or functions as possible on a semiconductor chip.
  • Such increases in the degree of integration have a directly favorable effect on the costs, the reliability, etc. of the products produced from them.
  • US Pat. No. 3,631,311 deals with an integrated semiconductor circuit arrangement which provides a transistor with a base leakage resistance integrated directly therewith.
  • the resistance area extends on one side into the surrounding insulation area, whereby an external resistance connection can also be saved.
  • the leakage resistance integrated together with the transistor base is known as a pinch or. Dumbbell resistor designed.
  • Such a pinch resistor is a double-diffused resistor, in which the line channel of the actual resistance region is constricted in its cross section by introducing a further doping region of the opposite conductivity type. Relatively high-resistance values can thus be achieved without this being associated with an otherwise inevitably high semiconductor area requirement when the sheet resistance is used.
  • the invention solves the problem of specifying a space-saving integrated semiconductor arrangement for a diode / resistor configuration which, in particular, requires as few external connection contacts and interconnection conductors as possible and can be produced by means of conventional method steps.
  • the resistance should be able to be designed for high resistance values, as are required for leakage resistors and have the lowest possible parasitic capacitance.
  • the invention provides for the extremely extensive integration of a Schottky diode with a pinch resistor connected thereto, the pinch-off doping region of which also represents the cathode connection doping region of the Schottky diode.
  • the Schottky contact is formed simultaneously with the resistance connection by a common metal electrode overlapping the associated P / N junction.
  • the additional contact for the resistor can also be saved by extending the resistance area into the surrounding isolation doping area, via which the corresponding voltage supply then takes place when the resistor is used as a discharge resistor.
  • the pinch resistor has a P feasibled doped resistance area within a surrounding N-type semiconductor material in a surrounding area, that the pinch-doping region of the pinch resistor is arranged relatively between the two ends of the resistance area highly doped N conductive area, the penetration depth of which is less than that of the resistance area.
  • the diode / resistor configuration constructed according to the measures of the invention is distinguished by an extremely small need for active semiconductor area, since it manages with a minimum of external connections and interconnections while avoiding intermediate isolation.
  • the available high resistance value with only a small parasitic capacitive influence allows a versatile application, for. B. as a isolation diode / leakage resistance combination with low own power dissipation.
  • the diode D is a Schottky diode with the anode connection A and the cathode connection K.
  • the resistor R With the anode connection A, the resistor R is connected, to the other connection of which a reference voltage VR can be applied. If the resistor R is used as a bleeder resistor, VR can, for example, be the most negative voltage occurring in the circuit.
  • the symbol used for the resistor R in FIG. 1 is intended to indicate that this is a (known pinch resistor with a pinch-off region in the course of the resistor area).
  • FIG. 2A now shows a particularly advantageous exemplary embodiment for the highly integrated embodiment of the circuit shown in FIG. 1 as a semiconductor arrangement.
  • FIG. 2B additionally shows a cross-sectional illustration along the section line designated in FIG. A2.
  • the cross-sectional illustration in FIG. 2B is expanded in the sense of a perspective illustration.
  • the diode / resistor combination according to the invention can be produced by means of conventional methods which are conventional in the field of integrated semiconductor circuits, which is why there is no need to go into this in the present context.
  • buried doping regions in the form of the known subcollector regions can be provided in the substrate 1, but are not shown in the present case for the sake of clarity.
  • an epitaxial layer of the opposite conductivity type is usually applied to the substrate 1 using known epitaxy methods and is divided into individual, delimited surrounding areas 3 made of N-conducting semiconductor material by frame-shaped separation doping areas 2. These delimited surrounding areas 3 of the epitaxial layer serve in a known manner to accommodate the semiconductor components to be formed therein.
  • both the diode D and the resistor R integrated therewith are arranged in such a delimited surrounding area 3 made of N-conducting semiconductor material.
  • the resistor R consists of the elongated P conductively doped resistance region 4, the cross section of which is constricted in the manner customary for pinch resistors by introducing a constriction doping region 5 of the opposite conductivity type, in the present case made of N + conductive semiconductor material.
  • the constriction doping region has a smaller penetration depth than the resistance region 4.
  • the pinch-up doping region 5 extends beyond the width of the resistance region 4 (at 6), so that there it is in connection with the semiconductor material surrounding the resistance region 4 in the surrounding region 3 of the same conductivity type.
  • the conventional doping methods such as diffusion or ion implantation, can be used to produce the resistance region 4 and the pinch-up doping region 5.
  • the resistance area 4 is equipped with a metal electrode A on a vein, in the exemplary embodiment of FIG. 2 at the right end.
  • This metal electrode A forms an ohmic contact with the P-conducting resistance region 4. It is particularly advantageous in the context of the present invention to design the metal electrode A as an overlapping contact, so that it also extends beyond the resistance region 4 into the surrounding N conductive material of the surrounding region 3. As a result, in the present case, a rectifying Schottky contact is formed on the N-conducting semiconductor material of the surrounding area 3 by the metal electrode A in addition to an ohmic contact in the resistance area 4.
  • connection contact formed as a metal electrode for the external connection.
  • This metal electrode is designated K because the cathode of the Schottky diode D is accessible from the outside.
  • the metal electrode K can consist of the same metal as the metal contact A, because the degree of doping of the cutoff Nürdot ists Society 5 is higher than the semiconductor material in the surrounding area 3, so that the metal electrode K forms an ohmic contact.
  • the production of the metal contact A and the metal electrode K can be carried out by means of conventional methods, for. B. by means of aluminum vapor deposition, sputtering, etc., take place. In this context, it should also be noted that both the formation of the doping regions and the metallizations can be carried out together with the corresponding method steps for the further circuit elements to be produced on the same semiconductor chip.
  • the P conductive resistance area 4 can be made simultaneously with the base doping, the pinch-up doping area 5 with the emitter doping and the contacting with the other metallizations for the connections and conductor tracks on the chip.
  • the circuit D shown in FIG. 1 completes the diode D with its external connections A and K and the resistor R connected to the anode connection A.
  • the resistor R as a bleed resistor for the most negative potential occurring in the circuit, the otherwise required contact on the resistance region 4 can finally be saved according to a special embodiment of the invention in that the resistance region 4 with its other end, in the exemplary embodiment shown on the left to extends into the separation doping area 2 surrounding the surrounding area 3. Since the isolation doping regions 2 for the formation of blocked P / N junctions are generally at the lowest potential occurring in the circuit, the resistor R receives the corresponding voltage supply at its connection for the reference potential VR, without providing a special area-consuming additional contact to have to.
  • the diode / resistor combination shown in FIG. 1 can thus be implemented with an extraordinarily high integration density and only two external contacts, which, compared to a conventional design of such a circuit part, results in a considerable saving in area, which is based on a true-to-scale area comparison with the aid of FIG .3 should be illustrated.
  • FIG. 3 shows a conventional, integrated semiconductor arrangement for the circuit part shown in FIG. 1.
  • the same extension parts were used.
  • the same design guidelines, ie distance regulations, minimum area sizes etc. were used as in Fig. 2A.
  • the pinch resistor with its P-conducting resistance region 9 and the pinch-off doping region 10 and the two outer connections 11 and 12 is formed in a first insulated semiconductor region 8.
  • the Schottky diode is made in a second semiconductor region 13 from N conductive semiconductor material.
  • the metal electrode 14 forms the Schottky junction for the anode, while the further metal electrode 15 on the N + conductive doping region 16 forms an ohmic contact for the cathode of the Schottky diode.
  • a comparison of the area of the conventional embodiment according to FIG. 3 with the embodiment according to a preferred embodiment of the invention according to FIG. 2A results in an area saving of approximately 54% if the diode / resistor configuration according to FIG. 1 is integrated according to the invention.
  • FIG. 4 shows as an application example the use of the diode / resistor configuration according to the invention in the control area of a semiconductor memory.
  • FIG. 4 shows a section of a memory arrangement which is limited to a bit line pair BLO, BL1.
  • BLO bit line pair
  • BL bit line pair
  • all word and bit selection lines must be charged or brought to defined DC voltage potentials for the idle state after each access period by means of a clocked control logic.
  • a series of transistors are provided as current sinks and current sources, which are controlled by a schematically indicated circuit 17. Via the circuit 17, the base connections of the transistors 18, 19 and 20 can be selected in the absence of the reference potential VR, z. B. the smallest potential occurring in the circuit can be pulled down. The voltage drop across the isolating diode is neglected.
  • Each such group of transistors belonging to a bit line pair or to a word line can be decoupled from the corresponding transistors of another bit line pair or another word line by means of the diode / resistor configuration shown in the boxed area 21 according to FIG. 1.
  • all decoupling diodes D are biased in the reverse direction on the chip concerned, so that write-in or. Readout processes can be carried out.
  • a leakage resistance R is also parallel to the Anode connection of the decoupling diode D is provided. So that only the lowest possible current can flow through the bleeder resistor in the selection case, the bleeder resistor R should have the highest possible resistance value and the most parasitic capacitance. These properties go directly into the switching times that can be achieved and the power loss.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Claims (9)

1. Dispositif semi-conducteur à haute densité d'intégration comportant une structure diode-résistance dans laquelle la résistance (R) fait fonction de résistance de pincement, la région dopée de pincement (5) est plus grande que la dimension transversale de sa région de résistance (4) formant le canal conducteur, caractérisé en ce que la région dopée de pincement (5) constitue en même temps la région dopée de contact de cathode pour la diode de Schottky (D), que sur la région de résistance (4), écartée de la région dopée de pincement (5), est prévu un contact métallique (A) dépassant la surface de la région de résistance (4) qui forme, avec la région de résistance (4), un contact ohmique et, avec le matériau semi-conducteur (3) entourant la région de résistance (4) qui est du type de conductivité opposé, une jonction redresseuse (à 7) qui constitue l'anode de la diode de Schottky, et enfin qu'à une extrémité de la région de résistance (4) est prévu un contact pour son potentiel électrique.
2. Dispositif semi-conducteur à haute densité d'intégration selon la revendication 1, caractérisé en ce qu'une borne de connexion (K) est prévue sur la région dopée de pincement (5) pour constituer le contact de cathode de la diode de Schottky (D).
3. Dispositif semi-conducteur à haute densité d'intégration selon la revendication 2, caractérisé en ce que la région dopée de pincement (5) par rapport au matériau semi-conducteur entourant (3) du même type de conductivité a une concentration de dopage plus élevée, au moins suffisamment élevée pour que la borne de connexion du contact de cathode de la diode de Schottky, faisant fonction d'électrode métallique (K), forme un contact ohmique avec la région dopée de pincement (5).
4. Dispositif semi-conducteur à haute densité d'intégration selon l'une quelconque des revendications 1 à 3, caractérisé en ce que la région de résistance (4) est disposée de sorte qu'elle pénètre à une extrémité dans une région dopée d'isolation (2) et de même type de conductivité, cette dernière région étant prévue en particulier pour assurer l'isolation électrique de la structure diode-résistance, et en ce que la région dopée de séparation (2) fournit à la région de résistance (4) son potentiel électrique (VR).
5. Dispositif semi-conducteur à haute densité d'intégration selon l'une quelconque des revendications 1 à 4, caractérisé en ce que la résistance (R) constitue une résistance de décharge de forte valeur disposée en parallèle avec la diode de Schottky (D).
6. Dispositif semi-conducteur à haute densité d'intégration selon la revendication 5, caractérisé en ce que la résistance de décharge (R) bloque, lorsque la diode de Schottky (D) est polarisée en inverse, la montée du potentiel de l'anode de la diode de Schottky et l'empêche de devenir conductrice.
7. Dispositif semi-conducteur à haute densité d'intégration selon l'une quelconque des revendications 1 à 6, caractérisé en ce que la structure diode-résistance est introduite, dans les lignes de sélection d'une configuration de cellules de mémoire (Figure 4).
8. Dispositif semi-conducteur à haute densité d'intégration selon la revendication 7, caractérisé en ce que grâce à la structure diode-résistance, les lignes de sélection peuvent être connectées à, ou déconnectées des circuits supplémentaires pour la charge ou décharge contrôlée des lignes de sélection pendant ou entre les opérations d'accès aux cellules mémoire.
9. Dispositif semi-conducteur à haute densité d'intégration selon l'une quelconque des revendications 1 à 8, caractérisé en ce que la résistance de pincement est constituée par une région résistive (4) du type de conductivité P, entourée par une région (3) du type de conductivité N, que la région de pincement (5) forme une région relativement fortement dopée du type de conductivité N, qui est disposée entre les deux extrémités de la région résistive (4), sa profondeur de jonction étant inférieure à celle de la région résistive (4) et qu'enfin un contact métallique (A) est disposé sur une extrémité de la région résistive (4).
EP78100195A 1977-07-26 1978-06-19 Dispositif semiconducteur à haute densité d'intégration comprenant une structure diode-résistance Expired EP0000472B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19772733615 DE2733615A1 (de) 1977-07-26 1977-07-26 Hochintegrierte halbleiteranordnung enthaltend eine dioden-/widerstandskonfiguration
DE2733615 1977-07-26

Publications (2)

Publication Number Publication Date
EP0000472A1 EP0000472A1 (fr) 1979-02-07
EP0000472B1 true EP0000472B1 (fr) 1981-02-11

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EP78100195A Expired EP0000472B1 (fr) 1977-07-26 1978-06-19 Dispositif semiconducteur à haute densité d'intégration comprenant une structure diode-résistance

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US (1) US4170017A (fr)
EP (1) EP0000472B1 (fr)
JP (1) JPS5424585A (fr)
DE (2) DE2733615A1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355014A (en) * 1993-03-03 1994-10-11 Bhasker Rao Semiconductor device with integrated RC network and Schottky diode
US6229181B1 (en) 1999-04-30 2001-05-08 Digital Devices, Inc. Semiconductor device and method of forming a semiconductor structure to provide electrostatic discharge protection
DE202008004595U1 (de) 2008-04-02 2008-07-17 Wastec B.V. Müllbehälter mit einer elektronischen Dateneinrichtung
US8709833B2 (en) 2011-12-22 2014-04-29 International Business Machines Corporation Measuring current and resistance using combined diodes/resistor structure to monitor integrated circuit manufacturing process variations
US10982399B1 (en) * 2020-04-16 2021-04-20 EBJM Industries, LLC Cable barrier system for use with cable barrier management system including turnbuckle subsystem, and method
WO2024137722A2 (fr) * 2022-12-19 2024-06-27 Peiching Ling Structures semi-conductrices et dispositifs de mémoire et leurs procédés de fabrication

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1574651C3 (de) * 1968-03-01 1976-01-02 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithisch integrierte Flip-Flop-Speicherzelle
US3631311A (en) * 1968-03-26 1971-12-28 Telefunken Patent Semiconductor circuit arrangement with integrated base leakage resistance
US3909837A (en) * 1968-12-31 1975-09-30 Texas Instruments Inc High-speed transistor with rectifying contact connected between base and collector
US3631309A (en) * 1970-07-23 1971-12-28 Semiconductor Elect Memories Integrated circuit bipolar memory cell
US3940785A (en) * 1974-05-06 1976-02-24 Sprague Electric Company Semiconductor I.C. with protection against reversed power supply
US3971060A (en) * 1974-07-12 1976-07-20 Texas Instruments Incorporated TTL coupling transistor
US4005469A (en) * 1975-06-20 1977-01-25 International Business Machines Corporation P-type-epitaxial-base transistor with base-collector Schottky diode clamp

Also Published As

Publication number Publication date
JPS5424585A (en) 1979-02-23
JPS5725982B2 (fr) 1982-06-02
DE2733615A1 (de) 1979-02-01
US4170017A (en) 1979-10-02
DE2860462D1 (en) 1981-03-26
EP0000472A1 (fr) 1979-02-07

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