EP0000114A1 - Procédé pour fabriquer un circuit logique intégré comportant des transistors bipolaires et circuit intégré fabriqué à l'aide de ce procédé. - Google Patents

Procédé pour fabriquer un circuit logique intégré comportant des transistors bipolaires et circuit intégré fabriqué à l'aide de ce procédé. Download PDF

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Publication number
EP0000114A1
EP0000114A1 EP78100005A EP78100005A EP0000114A1 EP 0000114 A1 EP0000114 A1 EP 0000114A1 EP 78100005 A EP78100005 A EP 78100005A EP 78100005 A EP78100005 A EP 78100005A EP 0000114 A1 EP0000114 A1 EP 0000114A1
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EP
European Patent Office
Prior art keywords
zone
buried
epitaxial layer
over
layer
Prior art date
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Granted
Application number
EP78100005A
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German (de)
English (en)
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EP0000114B1 (fr
Inventor
David L. Bergeron
Geoffrey B. Stephens
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8226—Bipolar technology comprising merged transistor logic or integrated injection logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]
    • H01L27/0244—I2L structures integrated in combination with analog structures
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/918—Light emitting regenerative switching device, e.g. light emitting scr arrays, circuitry
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/966—Selective oxidation of ion-amorphousized layer

Definitions

  • the invention relates generally to a method for producing integrated semiconductor circuits and, in particular, for producing bipolar transistors with different voltage properties on the same semiconductor die.
  • Integrated logic 1 2 L circuits with charge carrier injection operate at a relatively low signal level of 1 volt. It has been very difficult to establish a signal transmission between different I 2 L semiconductor wafers or chips at this low signal level. Additional voltage amplifier circuits require a higher breakdown voltage at the base / collector transition of the vertical bipolar transistor used in the chip output driver stage at the input / output of the chip. However, if one increases the base-collector layer thickness of a down-injecting vertical bipolar transistor for output driver stages, the result is that the upward-injection vertical bipolar transistors of the internal logic 1 2 L circuits have a very low emitter efficiency and have a very large charge storage capacity, since both types of components have to be manufactured simultaneously in every practical and economical manufacturing process. Therefore, practically implemented 1 2 L circuits have the disadvantage that they either have fast internal logic circuits and output driver stages operating at low voltage or slower internal logic circuits with output driver stages operating at higher voltage.
  • the invention discloses a method for simultaneously manufacturing two different transistors for I 2 L circuits on a single semiconductor die, one type of circuit operating at low signal voltages and the other type of circuit operating as output driver stages at relatively high signal voltages.
  • a vertically arranged NPN transistor - which, as is common with I 2 L (Integrated Injection Logic) circuits, works with upward injection, is built with a thinner epitaxially grown layer between the buried sub-emitter and the base zone than that with thicker epitaxially grown layer between the buried sub-collector and the base zone down injecting vertical NPN transistor of the output driver stage or input stage on the same semiconductor die.
  • a locally thinned zone can be formed in which the base and collector structures can subsequently be fabricated using the same process steps used to form base and emitter structures in the output driver stages downward injecting NTN transistors are formed.
  • Figs. 1A and 2A show the formation of an N + -type Subemitters 4 and a N + - type subcollector 6 in a P-type substrate 2 for injecting the upward or downward injecting transistor.
  • the N -subzones 4 and 6 are produced by a conventional arsenic diffusion through openings which have been produced by conventional photolithographic processes in a SiO 2 mask thermally grown on the P-type substrate 2.
  • the P-type substrate has a specific resistance of 5 - 20 Ohm / cm.
  • the N -conducting zones 4 and 6 have a surface concentration of more than 10 20 per cm 3 and a layer thickness of 2.5 ⁇ m. Zones 4 and 6 are reoxidized before formation of buried P -conducting zones 8.
  • Fig. 1B and 2B show the formation of P + -type buried isolation regions 8 for the up-injection and the down-injection transistor, respectively.
  • the buried P + -conducting zones 8 are produced by conventional boron diffusion through openings which were produced by conventional photolithographic processes in a cumulative, thermally generated SiO 2 mask layer.
  • the P -conducting zones 8 have a surface concentration of more than 10 20 cm -3 and a layer thickness of 3.0 ⁇ m.
  • Fig. 1C and 2C show the formation of an epitaxial layer 10 for the up-and-down injection transistor.
  • an N-conducting layer 10 is grown epitaxially to a thickness of 3.2 ⁇ m and a doping concentration of 2 ⁇ 10 16 j e cm 3 .
  • the buried insulation diffusions 8 expand by diffusion into the parts 8 ′ in the substrate 2 and parts 8 ′′ in the epitaxial layer 10.
  • a silicon dioxide layer 12 is then formed on the epitaxial layer 10.
  • the silicon dioxide layer 12 is thermally grown in an O 2 H 2 OO 2 atmosphere at 970 ° C. to a thickness of 300 nm.
  • Fig. 1D and 2D show the formation of a photoresist layer 14 over the silicon dioxide layer 12, which serves as a mask layer for the ion implantation.
  • an opening 16 is formed through the photoresist layer 14 and the silicon dioxide layer 12 to expose the surface of the epitaxial layer 10. No corresponding opening is produced in the downward-injection vertical transistor shown in FIG. 2D.
  • the introduction of damage in the crystal structure of the exposed zone of the epitaxial layer 10 is intended to increase the reactive oxidation rate of the surface and the percentage of Si consumed during a subsequent oxidation process step.
  • the implantation is carried out with a conventional ion implantation device, the acceleration voltage of which is in the range between 10 and 400 KeV.
  • the photoresist layer 14 and the silicon dioxide layer 12 are chosen so thick that the penetration of the ion beam 18 is covered in the areas of the epitaxial layer 10 that are not exposed through an opening 16.
  • Possible Thicknesses of the photoresist layer, the silicon dioxide layer, the type of ions implanted and the acceleration voltage are summarized in Table 1.
  • Fig. 1E and 2E show the formation of a silicon dioxide layer 20 after removal of the photoresist mask 14. It can be seen that the depth of penetration of the silicon dioxide layer 20 is greater than any increase in the thickness of the already existing silicon dioxide layer 12, since that in the epitaxial layer 10 due to the ion implantation with the ions 18 introduced damage to the crystal structure have increased the reactivity of the exposed epitaxial layer 10 in the oxidation reaction.
  • This thermal oxidation is carried out at 970 ° C. in an H 2 0-0 2 atmosphere with a cycle time determined in such a way that the zone in the silicon layer 10 lying below the opening 16 and damaged in its crystal structure is oxidized through.
  • Table 1 gives layer thicknesses for thermally grown silicon dioxide zones 20 for steam cycles which have been determined in such a way that the oxidation rate is three times as high as that of the undamaged part of the silicon layer 10. Significant radiation damage is within twice the normal deviation from the maximum value of the distribution of the implanted ions.
  • Fig. 1F and 2F show the formation of the reoxidized layer 22 of silicon dioxide for up and down injecting transistors after removing the existing oxide layer 12 and oxide layer 20 by stripping the oxides.
  • the oxide layer 12 and the oxide layer 20 are chemically removed by etching with hydrofluoric acid.
  • the new oxide layer 22 is formed in an O 2 -H 2 OO 2 atmosphere at 970 ° C. with a cycle time such that a layer thickness of 300 nm is achieved.
  • the thickness of the epitaxial layer 10 'of the up-injection transistor above the subemitter 4' where the oxide layer 20 was formed is less than that of the corresponding epitaxial layer 10 over the subcollector 6 'of the downward injecting transistor.
  • the epitaxial layer 10 ′ has a thickness of approximately 2.8 ⁇ m, corresponding to a thickness of 200 nm to the thermally grown oxide layer 20, while the epitaxial layer 10 has a thickness of 2.89 ⁇ m.
  • the epitaxial layer 10 ′ has a thickness of approximately 2.65 ⁇ m, corresponding to a thickness of 500 nm for the thermally grown oxide layer 20, while the epitaxial layer 10 has a thickness of 2.85 ⁇ m.
  • Figs. 1G and 2G is the formation of P-type base zones 24 and 26 for the up and down injecting transistor, respectively. shown.
  • the P-type downward region 8 "' is also formed.
  • the P-type zones 24, 26 and 8"' are produced by conventional photolithographic processes and diffusion.
  • the P-type zones 24, 26 and 8 "' have a surface concentration of approximately 5 ⁇ 10 18 atoms / cm3 and a layer thickness of approximately 1.2 ⁇ m.
  • the P-type zones 24, 26 and 8"' are then in O 2 oxidized at about 1000 ° C to form an approximately 110 nm thick oxide layer ..
  • Fig. 1H and 2H show the formation of contact holes 34 and 28 through the oxide layer 22 to produce the emitter and collector diffusion regions 42 and 40 in the downward and upward injecting transistor, respectively.
  • the openings 28, 30, 32, 34, 36 and 38 in the passivating oxide layer 22 are simultaneously formed by conventional photographic and oxide etching processes.
  • Fig. 11 and 21 show the finished up and down injecting transistors.
  • an N + -type collector 40 is formed, while in 21, an N + -type emitter 42 is formed.
  • the N-dividing zones 40, 42, 44 and 46 are produced by first applying a photoresist barrier layer 48, the openings of which overlap the previously defined oxide openings 28, 32, 34 and 38, while the openings 30 and 36 are blocked.
  • the N + -conducting zones 40, 42, 44 and 46 are generated by ion implantation of arsenic ions through the oxide openings 28, 32, 34 and 38 at an energy of 50 KeV and a dosage of 8 x 10 15 cm -2 .
  • the photoresist layer 48 is then removed and the arsenic is activated on subsequent tempering for 50 minutes at 1050 ° C. and then diffuses to the desired functional depth of 0.6 ⁇ m.
  • the sequence of procedural steps according to FIGS. 1A through 11 and 2A through 21 are for a process performed on a single semiconductor die, forming I 2 L circuits operating at low signal voltage and output driver stages operating at relatively high signal voltages.
  • 11 is normally used in I 2 L circuits and is formed with a thin epitaxial layer 50 'between the buried sub-emitter 4' and the base zone 24, while a thicker epitaxial layer 50 the buried sub-collector 6 '. from the base region 26 of the downward injecting vertical NPN transistor in FIG.
  • the charge stored in the epitaxial zones 50 ', 50 is proportional to the square of the thickness of these zones. However, this means that for a thermally grown oxide layer 20 with a thickness of 500 nm and with an upward diffusion of the subemitter 4 'of 1.4 ⁇ m, the stored charge in the zone 50' with a thickness of 50 nm is approximately 25 times smaller than that stored in the zone 50 with a thickness of 250 nm Charge. It can be shown that an upward injecting transistor has an injection efficiency that is proportional. the average doping concentration in the sub-emitter zone is 4 'and 50'. Since the epitaxial layer 50 'is lightly doped, the average doping concentration in the sub-emitter regions 4' and 50 'is increased by keeping the thickness of the lightly doped layer 50' small.
  • the breakdown voltages from collector to base and from collector to emitter are directly proportional to the thickness of the lightly doped epitaxial layer 50.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
EP78100005A 1977-06-16 1978-06-01 Procédé pour fabriquer un circuit logique intégré comportant des transistors bipolaires et circuit intégré fabriqué à l'aide de ce procédé. Expired EP0000114B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US807286 1977-06-16
US05/807,286 US4157268A (en) 1977-06-16 1977-06-16 Localized oxidation enhancement for an integrated injection logic circuit

Publications (2)

Publication Number Publication Date
EP0000114A1 true EP0000114A1 (fr) 1979-01-10
EP0000114B1 EP0000114B1 (fr) 1980-04-30

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EP78100005A Expired EP0000114B1 (fr) 1977-06-16 1978-06-01 Procédé pour fabriquer un circuit logique intégré comportant des transistors bipolaires et circuit intégré fabriqué à l'aide de ce procédé.

Country Status (4)

Country Link
US (1) US4157268A (fr)
EP (1) EP0000114B1 (fr)
JP (1) JPS546784A (fr)
DE (1) DE2857616D1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0012545A1 (fr) * 1978-12-04 1980-06-25 Western Electric Company, Incorporated Circuit semiconducteur intégré et procédé pour sa fabrication
FR2495379A1 (fr) * 1980-12-01 1982-06-04 Hitachi Ltd Circuit integre a semiconducteurs et procede de fabrication de ce dernier
US4677456A (en) * 1979-05-25 1987-06-30 Raytheon Company Semiconductor structure and manufacturing method
WO2014014125A1 (fr) * 2012-07-20 2014-01-23 Fujifilm Corporation Procédé de gravure, procédé de production d'un substrat semi-conducteur et dispositif à semi-conducteur l'utilisant

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JPS55156366A (en) * 1979-05-24 1980-12-05 Toshiba Corp Semiconductor device
US4493740A (en) * 1981-06-01 1985-01-15 Matsushita Electric Industrial Company, Limited Method for formation of isolation oxide regions in semiconductor substrates
US4586243A (en) * 1983-01-14 1986-05-06 General Motors Corporation Method for more uniformly spacing features in a semiconductor monolithic integrated circuit
US4544940A (en) * 1983-01-14 1985-10-01 General Motors Corporation Method for more uniformly spacing features in a lateral bipolar transistor
JPS6031231A (ja) * 1983-07-29 1985-02-18 Toshiba Corp 半導体基体の製造方法
JPS6127669A (ja) * 1984-07-18 1986-02-07 Hitachi Ltd 半導体装置
US5635861A (en) * 1995-05-23 1997-06-03 International Business Machines Corporation Off chip driver circuit
US6113733A (en) * 1996-11-08 2000-09-05 Matsushita Electric Industrial Co., Ltd. Apparatus and method for optical evaluation, apparatus and method for manufacturing semiconductor device, method of controlling apparatus for manufacturing semiconductor device, and semiconductor device
DE102004055183B3 (de) * 2004-11-16 2006-07-13 Atmel Germany Gmbh Integrierte Schaltung und Verfahren zur Herstellung einer integrierten Schaltung auf einem Halbleiterplättchen
DE102004055213B4 (de) * 2004-11-16 2009-04-09 Atmel Germany Gmbh Verfahren zur Herstellung einer integrierten Schaltung auf einem Halbleiterplättchen

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DE2455347A1 (de) * 1974-11-22 1976-05-26 Itt Ind Gmbh Deutsche Monolithisch integrierte festkoerperschaltung und herstellungsverfahren
FR2290758A1 (fr) * 1974-11-08 1976-06-04 Itt Methode de diffusion planaire pour circuit integre en logique a injection
US3966501A (en) * 1973-03-23 1976-06-29 Mitsubishi Denki Kabushiki Kaisha Process of producing semiconductor devices
FR2319197A1 (fr) * 1975-07-22 1977-02-18 Itt Circuit integre en logique a injection

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US3884732A (en) * 1971-07-29 1975-05-20 Ibm Monolithic storage array and method of making
DE2137976C3 (de) * 1971-07-29 1978-08-31 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithischer Speicher und Verfahren zur Herstellung
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Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
US3966501A (en) * 1973-03-23 1976-06-29 Mitsubishi Denki Kabushiki Kaisha Process of producing semiconductor devices
FR2290758A1 (fr) * 1974-11-08 1976-06-04 Itt Methode de diffusion planaire pour circuit integre en logique a injection
DE2455347A1 (de) * 1974-11-22 1976-05-26 Itt Ind Gmbh Deutsche Monolithisch integrierte festkoerperschaltung und herstellungsverfahren
FR2319197A1 (fr) * 1975-07-22 1977-02-18 Itt Circuit integre en logique a injection

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0012545A1 (fr) * 1978-12-04 1980-06-25 Western Electric Company, Incorporated Circuit semiconducteur intégré et procédé pour sa fabrication
US4677456A (en) * 1979-05-25 1987-06-30 Raytheon Company Semiconductor structure and manufacturing method
FR2495379A1 (fr) * 1980-12-01 1982-06-04 Hitachi Ltd Circuit integre a semiconducteurs et procede de fabrication de ce dernier
WO2014014125A1 (fr) * 2012-07-20 2014-01-23 Fujifilm Corporation Procédé de gravure, procédé de production d'un substrat semi-conducteur et dispositif à semi-conducteur l'utilisant

Also Published As

Publication number Publication date
DE2857616D1 (en) 1980-06-12
US4157268A (en) 1979-06-05
JPS546784A (en) 1979-01-19
EP0000114B1 (fr) 1980-04-30

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