DE69925569D1 - Speichersteuerungsvorrichtung und -verfahren - Google Patents

Speichersteuerungsvorrichtung und -verfahren

Info

Publication number
DE69925569D1
DE69925569D1 DE69925569T DE69925569T DE69925569D1 DE 69925569 D1 DE69925569 D1 DE 69925569D1 DE 69925569 T DE69925569 T DE 69925569T DE 69925569 T DE69925569 T DE 69925569T DE 69925569 D1 DE69925569 D1 DE 69925569D1
Authority
DE
Germany
Prior art keywords
control device
memory control
memory
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69925569T
Other languages
English (en)
Other versions
DE69925569T2 (de
Inventor
Chikara Gotanda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69925569D1 publication Critical patent/DE69925569D1/de
Application granted granted Critical
Publication of DE69925569T2 publication Critical patent/DE69925569T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/63—Generation or supply of power specially adapted for television receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
    • H04N21/4305—Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/443—OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB
    • H04N21/4436—Power management, e.g. shutting down unused components of the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Dram (AREA)
  • Power Sources (AREA)
  • Circuits Of Receivers In General (AREA)
DE69925569T 1998-10-29 1999-10-25 Speichersteuerungsvorrichtung und -verfahren Expired - Lifetime DE69925569T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP30817298 1998-10-29
JP30817298 1998-10-29
PCT/JP1999/005870 WO2000026754A1 (en) 1998-10-29 1999-10-25 Memory controller and method of memory control

Publications (2)

Publication Number Publication Date
DE69925569D1 true DE69925569D1 (de) 2005-07-07
DE69925569T2 DE69925569T2 (de) 2005-11-10

Family

ID=17977779

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69925569T Expired - Lifetime DE69925569T2 (de) 1998-10-29 1999-10-25 Speichersteuerungsvorrichtung und -verfahren

Country Status (8)

Country Link
US (1) US6678832B1 (de)
EP (1) EP1042711B1 (de)
KR (1) KR100367634B1 (de)
CN (1) CN1329796C (de)
AU (1) AU751655B2 (de)
DE (1) DE69925569T2 (de)
MY (1) MY122426A (de)
WO (1) WO2000026754A1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7089438B2 (en) * 2002-06-25 2006-08-08 Micron Technology, Inc. Circuit, system and method for selectively turning off internal clock drivers
JP4005909B2 (ja) * 2002-12-26 2007-11-14 スパンション インク 半導体記憶装置、および半導体記憶装置の制御方法
US7196562B1 (en) * 2003-08-26 2007-03-27 Integrated Device Technology, Inc. Programmable clock drivers that support CRC error checking of configuration data during program restore operations
JP4526841B2 (ja) * 2004-03-09 2010-08-18 ルネサスエレクトロニクス株式会社 メモリ制御装置およびこれを備えたデータ処理システム
DE102004052268B4 (de) * 2004-10-27 2016-03-24 Polaris Innovations Ltd. Halbleiterspeichersystem und Verfahren zur Datenübertragung zwischen einem Speichercontroller und einem Halbleiterspeicher
US8165024B2 (en) * 2008-04-03 2012-04-24 Alcatel Lucent Use of DPI to extract and forward application characteristics
JP2012515376A (ja) 2009-01-12 2012-07-05 ラムバス・インコーポレーテッド クロック転送低電力シグナリングシステム
KR101581414B1 (ko) 2009-02-05 2015-12-30 삼성전자주식회사 전력 소모 감소를 위한 재구성 가능 프로세서 및 그 동작 방법
WO2011056729A2 (en) * 2009-11-05 2011-05-12 Rambus Inc. Interface clock management
FI3325183T3 (fi) 2015-07-23 2024-02-08 Renmatix Inc Menetelmä likaavan aineen poistamiseksi paineastiasta
US11132307B2 (en) 2018-05-25 2021-09-28 Rambus Inc. Low latency memory access

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5157492A (en) * 1990-04-30 1992-10-20 Thomson Consumer Electronics, Inc. Sync validity detecting utilizing a microcomputer
JPH0628053A (ja) * 1992-07-09 1994-02-04 Fujitsu Ltd スタンバイモードを有する電子機器
US5452434A (en) * 1992-07-14 1995-09-19 Advanced Micro Devices, Inc. Clock control for power savings in high performance central processing units
JP2729012B2 (ja) 1992-08-03 1998-03-18 富士通株式会社 マイクロプロセッサの低消費電力化回路
US5473767A (en) * 1992-11-03 1995-12-05 Intel Corporation Method and apparatus for asynchronously stopping the clock in a processor
US5603036A (en) * 1993-02-19 1997-02-11 Intel Corporation Power management system for components used in battery powered applications
JPH07191954A (ja) 1993-12-27 1995-07-28 Matsushita Electric Ind Co Ltd マイクロコンピュータシステム
US5524249A (en) * 1994-01-27 1996-06-04 Compaq Computer Corporation Video subsystem power management apparatus and method
JP3647481B2 (ja) 1994-04-28 2005-05-11 富士通株式会社 マイクロコントローラ
JPH0836499A (ja) 1994-07-21 1996-02-06 Mitsubishi Denki Semiconductor Software Kk マイクロコンピュータ
US5615376A (en) * 1994-08-03 1997-03-25 Neomagic Corp. Clock management for power reduction in a video display sub-system
JPH08101657A (ja) * 1994-09-30 1996-04-16 Toshiba Corp コンピュータシステムおよびそのシステムにおけるｃｒｔディスプレイの消費電力制御方法
JP2924773B2 (ja) * 1996-03-28 1999-07-26 日本電気株式会社 位相同期システム
JPH1031530A (ja) 1996-07-16 1998-02-03 Hitachi Ltd 中央演算処理装置
JPH10105275A (ja) 1996-09-30 1998-04-24 Osaki Electric Co Ltd クロック出力装置
KR100283572B1 (ko) * 1997-02-24 2001-03-02 윤종용 Osd를 이용한 디스플레이 장치의 dpms 표시 방법
US5917350A (en) * 1997-03-28 1999-06-29 Cypress Semiconductor Corp. Asynchronous pulse discriminating synchronizing clock pulse generator with synchronous clock suspension capability for logic derived clock signals for a programmable device
KR100247586B1 (ko) * 1997-07-22 2000-03-15 윤종용 전원 공급 장치의 과도 현상 억제 회로
JP3927294B2 (ja) * 1997-10-03 2007-06-06 株式会社ルネサステクノロジ 半導体装置
KR100578112B1 (ko) * 1998-10-16 2006-07-25 삼성전자주식회사 메모리 클럭 신호를 제어하는 컴퓨터 시스템 및그 방법
JP2001078054A (ja) * 1999-09-08 2001-03-23 Mitsubishi Electric Corp 垂直同期分離回路
JP2002099270A (ja) * 2000-07-19 2002-04-05 Sharp Corp 同期信号発生回路及びそれを用いた画像表示装置及び同期信号生成方法

Also Published As

Publication number Publication date
EP1042711A1 (de) 2000-10-11
MY122426A (en) 2006-04-29
CN1277685A (zh) 2000-12-20
WO2000026754A1 (en) 2000-05-11
AU751655B2 (en) 2002-08-22
EP1042711B1 (de) 2005-06-01
CN1329796C (zh) 2007-08-01
DE69925569T2 (de) 2005-11-10
US6678832B1 (en) 2004-01-13
KR20010033509A (ko) 2001-04-25
KR100367634B1 (ko) 2003-01-10
AU6229599A (en) 2000-05-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP

8320 Willingness to grant licences declared (paragraph 23)