DE69840247D1 - Verfahren zur Herstellung eines verbundenen Substrates - Google Patents

Verfahren zur Herstellung eines verbundenen Substrates

Info

Publication number
DE69840247D1
DE69840247D1 DE69840247T DE69840247T DE69840247D1 DE 69840247 D1 DE69840247 D1 DE 69840247D1 DE 69840247 T DE69840247 T DE 69840247T DE 69840247 T DE69840247 T DE 69840247T DE 69840247 D1 DE69840247 D1 DE 69840247D1
Authority
DE
Germany
Prior art keywords
preparation
bonded substrate
bonded
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69840247T
Other languages
English (en)
Inventor
Tokio Takei
Susumu Nakamura
Kazushi Nakazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Application granted granted Critical
Publication of DE69840247D1 publication Critical patent/DE69840247D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
DE69840247T 1997-02-21 1998-02-20 Verfahren zur Herstellung eines verbundenen Substrates Expired - Lifetime DE69840247D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP05409897A JP3352902B2 (ja) 1997-02-21 1997-02-21 貼り合わせ基板の作製方法

Publications (1)

Publication Number Publication Date
DE69840247D1 true DE69840247D1 (de) 2009-01-08

Family

ID=12961157

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69840247T Expired - Lifetime DE69840247D1 (de) 1997-02-21 1998-02-20 Verfahren zur Herstellung eines verbundenen Substrates

Country Status (3)

Country Link
EP (1) EP0860862B1 (de)
JP (1) JP3352902B2 (de)
DE (1) DE69840247D1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3422225B2 (ja) * 1997-07-08 2003-06-30 三菱住友シリコン株式会社 貼り合わせ半導体基板及びその製造方法
JP3524009B2 (ja) * 1999-01-27 2004-04-26 信越半導体株式会社 Ｓｏｉウェーハおよびその製造方法
JP4675559B2 (ja) * 2003-10-03 2011-04-27 株式会社ディスコ 積層ウェーハの加工方法
FR2899594A1 (fr) 2006-04-10 2007-10-12 Commissariat Energie Atomique Procede d'assemblage de substrats avec traitements thermiques a basses temperatures
FR2935536B1 (fr) 2008-09-02 2010-09-24 Soitec Silicon On Insulator Procede de detourage progressif
FR2954585B1 (fr) * 2009-12-23 2012-03-02 Soitec Silicon Insulator Technologies Procede de realisation d'une heterostructure avec minimisation de contrainte
FR2957189B1 (fr) 2010-03-02 2012-04-27 Soitec Silicon On Insulator Procede de realisation d'une structure multicouche avec detourage post meulage.
FR2961630B1 (fr) 2010-06-22 2013-03-29 Soitec Silicon On Insulator Technologies Appareil de fabrication de dispositifs semi-conducteurs
US8338266B2 (en) 2010-08-11 2012-12-25 Soitec Method for molecular adhesion bonding at low pressure
FR2964193A1 (fr) 2010-08-24 2012-03-02 Soitec Silicon On Insulator Procede de mesure d'une energie d'adhesion, et substrats associes
CN109786234B (zh) * 2017-11-13 2021-06-04 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59175729A (ja) * 1983-03-25 1984-10-04 Toshiba Corp 半導体基板の研削装置
JP2658135B2 (ja) * 1988-03-08 1997-09-30 ソニー株式会社 半導体基板
JPH0719737B2 (ja) * 1990-02-28 1995-03-06 信越半導体株式会社 Ｓ０１基板の製造方法
JP2662495B2 (ja) * 1993-06-28 1997-10-15 住友シチックス株式会社 接着半導体基板の製造方法

Also Published As

Publication number Publication date
EP0860862A2 (de) 1998-08-26
EP0860862A3 (de) 2000-08-09
EP0860862B1 (de) 2008-11-26
JPH10242091A (ja) 1998-09-11
JP3352902B2 (ja) 2002-12-03

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Legal Events

Date Code Title Description
8328 Change in the person/name/address of the agent

Representative=s name: MURGITROYD & COMPANY, 48149 MUENSTER

8364 No opposition during term of opposition