DE69833600D1 - Digitale PLL Schaltung und Verfahren zur Signalrückgewinnung - Google Patents

Digitale PLL Schaltung und Verfahren zur Signalrückgewinnung

Info

Publication number
DE69833600D1
DE69833600D1 DE69833600T DE69833600T DE69833600D1 DE 69833600 D1 DE69833600 D1 DE 69833600D1 DE 69833600 T DE69833600 T DE 69833600T DE 69833600 T DE69833600 T DE 69833600T DE 69833600 D1 DE69833600 D1 DE 69833600D1
Authority
DE
Germany
Prior art keywords
pll circuit
digital pll
signal recovery
recovery
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69833600T
Other languages
English (en)
Other versions
DE69833600T2 (de
Inventor
Mitsuo Baba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69833600D1 publication Critical patent/DE69833600D1/de
Application granted granted Critical
Publication of DE69833600T2 publication Critical patent/DE69833600T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE69833600T 1997-12-04 1998-12-03 Digitale PLL-Schaltung und Verfahren zur Signalrückgewinnung Expired - Fee Related DE69833600T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP33447597 1997-12-04
JP33447597A JP3109465B2 (ja) 1997-12-04 1997-12-04 ディジタルｐｌｌ回路及び信号再生方法

Publications (2)

Publication Number Publication Date
DE69833600D1 true DE69833600D1 (de) 2006-04-27
DE69833600T2 DE69833600T2 (de) 2007-01-25

Family

ID=18277815

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69833600T Expired - Fee Related DE69833600T2 (de) 1997-12-04 1998-12-03 Digitale PLL-Schaltung und Verfahren zur Signalrückgewinnung

Country Status (5)

Country Link
US (1) US6556640B1 (de)
EP (1) EP0921654B1 (de)
JP (1) JP3109465B2 (de)
AU (1) AU9609098A (de)
DE (1) DE69833600T2 (de)

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US5978379A (en) 1997-01-23 1999-11-02 Gadzoox Networks, Inc. Fiber channel learning bridge, learning half bridge, and protocol
US7430171B2 (en) 1998-11-19 2008-09-30 Broadcom Corporation Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost
US6522671B1 (en) * 1999-05-10 2003-02-18 Nortel Networks Limited Protocol independent sub-rate device
KR100371300B1 (ko) * 1999-06-21 2003-02-06 샤프 가부시키가이샤 비트동기회로
IT1310666B1 (it) * 1999-08-03 2002-02-19 Cselt Centro Studi Lab Telecom Ricevitore per segnali a flusso discontinuo e relativo procedimento diricezione.
JP3391442B2 (ja) 1999-11-05 2003-03-31 日本電気株式会社 クロック識別再生回路及びクロック識別再生方法
JP4387078B2 (ja) * 2000-02-14 2009-12-16 富士通株式会社 光受信器
CA2354780A1 (en) * 2000-08-04 2002-02-04 Silicon Image, Inc. Digital display jitter correction apparatus and method
KR100346837B1 (ko) 2000-09-02 2002-08-03 삼성전자 주식회사 클럭 스큐에 의한 에러를 최소화하는 데이타 복원 장치 및그 방법
JP3622685B2 (ja) * 2000-10-19 2005-02-23 セイコーエプソン株式会社 サンプリングクロック生成回路、データ転送制御装置及び電子機器
JP4272515B2 (ja) * 2001-07-27 2009-06-03 株式会社アドバンテスト 位相補正回路
JP3785972B2 (ja) * 2001-09-06 2006-06-14 ティアック株式会社 信号処理回路
US7221723B2 (en) * 2001-11-27 2007-05-22 Agilent Technologies, Inc. Multi-phase sampling
JP2004015112A (ja) * 2002-06-03 2004-01-15 Mitsubishi Electric Corp クロック抽出回路
TW567668B (en) * 2002-08-12 2003-12-21 Realtek Semiconductor Corp Data recovery system and method thereof
CN100352194C (zh) * 2003-04-23 2007-11-28 华为技术有限公司 调节采样时钟保障同步数据可靠接收的方法及其装置
US7248194B2 (en) * 2003-06-04 2007-07-24 Koninklijke Philips Electronics N.V. Bit-detection arrangement and apparatus for reproducing information
US7221725B2 (en) * 2003-06-27 2007-05-22 Sigmatel, Inc. Host interface data receiver
US7265690B2 (en) * 2003-09-25 2007-09-04 Texas Instruments Incorporated Simplified data recovery from high speed encoded data
US7545898B2 (en) * 2004-02-13 2009-06-09 Broadcom Corporation System and method for clock rate determination
JP4282658B2 (ja) * 2004-12-09 2009-06-24 エルピーダメモリ株式会社 半導体装置
EP1832033A2 (de) * 2004-12-23 2007-09-12 Philips Intellectual Property & Standards GmbH Schnittstellenschaltung sowie verfahren zum empfangen und/oder decodieren von datensignalen
US7856578B2 (en) * 2005-09-23 2010-12-21 Teradyne, Inc. Strobe technique for test of digital signal timing
US7573957B2 (en) * 2005-09-23 2009-08-11 Teradyne, Inc. Strobe technique for recovering a clock in a digital signal
US7574632B2 (en) * 2005-09-23 2009-08-11 Teradyne, Inc. Strobe technique for time stamping a digital signal
US8363772B2 (en) * 2007-05-29 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for eliminating phase distortion in signals
US8018950B2 (en) 2008-03-17 2011-09-13 Wi-Lan, Inc. Systems and methods for distributing GPS clock to communications devices
WO2011004580A1 (ja) * 2009-07-06 2011-01-13 パナソニック株式会社 クロックデータリカバリ回路
JP5463976B2 (ja) 2010-03-11 2014-04-09 富士通株式会社 受信回路及びサンプリングクロック制御方法
TWI446181B (zh) * 2011-08-08 2014-07-21 Faraday Tech Corp 資料擷取的方法與相關裝置
JP5834936B2 (ja) * 2012-01-17 2015-12-24 ソニー株式会社 情報処理装置および情報処理装置の制御方法
US10887395B2 (en) * 2016-11-21 2021-01-05 Ecosteer Srl Processing signals from a sensor group
CN107333161B (zh) * 2017-08-29 2019-09-17 青岛海信电器股份有限公司 对vbo信号进行处理的方法、信号处理芯片以及电视机
CN116072165B (zh) * 2023-03-07 2023-06-23 长鑫存储技术有限公司 一种信号采样电路和存储器

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EP0299024A4 (en) * 1987-01-05 1990-11-28 Grumman Aerospace Corporation High speed data-clock synchronization processor
US4986073A (en) 1988-02-03 1991-01-22 Kanzaki Kokyukoki Mfg. Co., Ltd. Axle driving apparatus
US5146478A (en) 1989-05-29 1992-09-08 Siemens Aktiengesellschaft Method and apparatus for receiving a binary digital signal
JPH0422234A (ja) 1990-05-16 1992-01-27 Matsushita Electric Ind Co Ltd データ識別装置
JPH04319829A (ja) 1991-04-19 1992-11-10 Fujitsu Ltd 位相同期回路
US5400370A (en) 1993-02-24 1995-03-21 Advanced Micro Devices Inc. All digital high speed algorithmic data recovery method and apparatus using locally generated compensated broad band time rulers and data edge position averaging
JP2773669B2 (ja) 1995-03-01 1998-07-09 日本電気株式会社 ディジタルｐｌｌ回路
US5920600A (en) * 1995-09-18 1999-07-06 Oki Electric Industry Co., Ltd. Bit phase synchronizing circuitry for controlling phase and frequency, and PLL circuit therefor
KR0153952B1 (ko) * 1995-12-16 1998-11-16 양승택 고속 디지털 데이터 리타이밍 장치
JP3493111B2 (ja) * 1997-02-25 2004-02-03 株式会社東芝 半導体集積回路装置
US6266799B1 (en) * 1997-10-02 2001-07-24 Xaqti, Corporation Multi-phase data/clock recovery circuitry and methods for implementing same

Also Published As

Publication number Publication date
EP0921654A2 (de) 1999-06-09
JPH11168455A (ja) 1999-06-22
JP3109465B2 (ja) 2000-11-13
EP0921654A3 (de) 2003-07-09
US6556640B1 (en) 2003-04-29
EP0921654B1 (de) 2006-03-01
DE69833600T2 (de) 2007-01-25
AU9609098A (en) 1999-06-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee