DE60032089D1 - Schaltung und Verfahren zur Rückgewinnung von Synchronisationsinformation aus einem Signal - Google Patents

Schaltung und Verfahren zur Rückgewinnung von Synchronisationsinformation aus einem Signal

Info

Publication number
DE60032089D1
DE60032089D1 DE60032089T DE60032089T DE60032089D1 DE 60032089 D1 DE60032089 D1 DE 60032089D1 DE 60032089 T DE60032089 T DE 60032089T DE 60032089 T DE60032089 T DE 60032089T DE 60032089 D1 DE60032089 D1 DE 60032089D1
Authority
DE
Germany
Prior art keywords
circuit
signal
synchronization information
recovering synchronization
recovering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60032089T
Other languages
English (en)
Inventor
Francesco Rezzi
Hakan Ozdemir
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Application granted granted Critical
Publication of DE60032089D1 publication Critical patent/DE60032089D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6343—Error control coding in combination with techniques for partial response channels, e.g. recording
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/16—Digital recording or reproducing using non self-clocking codes, i.e. the clock signals are either recorded in a separate clocking track or in a combination of several information tracks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE60032089T 1999-09-30 2000-09-20 Schaltung und Verfahren zur Rückgewinnung von Synchronisationsinformation aus einem Signal Expired - Lifetime DE60032089D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/410,274 US6604204B1 (en) 1999-09-30 1999-09-30 Circuit and method for recovering synchronization information from a signal

Publications (1)

Publication Number Publication Date
DE60032089D1 true DE60032089D1 (de) 2007-01-11

Family

ID=23624010

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60032089T Expired - Lifetime DE60032089D1 (de) 1999-09-30 2000-09-20 Schaltung und Verfahren zur Rückgewinnung von Synchronisationsinformation aus einem Signal

Country Status (4)

Country Link
US (1) US6604204B1 (de)
EP (1) EP1089486B1 (de)
JP (1) JP2001148169A (de)
DE (1) DE60032089D1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001332035A (ja) * 2000-05-19 2001-11-30 Hitachi Ltd データ同期信号検出装置、及びこれを用いた信号処理装置、並びにこれらを備えた情報記録再生装置、並びにデータ同期信号検出方法とこの方法に使用される情報記録媒体
US7839594B2 (en) 2001-06-28 2010-11-23 Stmicroelectronics, Inc. Data-storage disk having few or no spin-up wedges and method for writing servo wedges onto the disk
US7830630B2 (en) * 2001-06-28 2010-11-09 Stmicroelectronics, Inc. Circuit and method for detecting the phase of a servo signal
US7054398B1 (en) 2001-07-18 2006-05-30 Marvell International Ltd. Method for selecting sync marks and sync mark detectors
US7430704B2 (en) * 2003-12-19 2008-09-30 Stmicroelectronics S.R.L. Trellis-based detection process and system
US7430680B2 (en) * 2005-01-19 2008-09-30 Broadcom Corporation System and method to align clock signals
US7596940B2 (en) 2005-03-22 2009-10-06 Pratt & Whitney Rocketdyne, Inc. Rocket engine nozzle and method of fabricating a rocket engine nozzle using pressure brazing
US9171571B2 (en) * 2006-02-24 2015-10-27 Stmicrolectronics, Inc. Read channel operable to calibrate a coefficient of a filter, such as an FIR filter, disposed before an interpolated-timing-recovery circuit, and related integrated circuit, system, and method
US7974034B1 (en) 2006-06-07 2011-07-05 Marvell International Ltd. Systems and methods for sync mark detection using correlation
JP4658097B2 (ja) * 2006-07-27 2011-03-23 パナソニック株式会社 パルス同期復調装置
GB2446183B (en) * 2007-01-31 2011-07-20 Hewlett Packard Development Co Method and apparatus for controlling motion of storage media
US20190273577A1 (en) * 2018-03-05 2019-09-05 Qualcomm Incorporated Self-synchronizing viterbi decoder

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5012856B1 (de) * 1969-11-27 1975-05-15
GB8715597D0 (en) * 1987-07-02 1987-08-12 Indep Broadcasting Authority Digital synchronisation
US5430744A (en) 1993-09-30 1995-07-04 International Business Machines Corporation Method and means for detecting partial response waveforms using a modified dynamic programming heuristic
US5384671A (en) * 1993-12-23 1995-01-24 Quantum Corporation PRML sampled data channel synchronous servo detector
US5448571A (en) * 1994-04-26 1995-09-05 International Business Machines Corporation Method and apparatus for determining byte synchronization within a serial data receiver
US5729396A (en) * 1995-05-12 1998-03-17 Cirrus Logic, Inc. Fault tolerant sync mark detector enabled relative to a frequency of an acquisition preamble for sampled amplitude recording
US5793548A (en) * 1995-05-12 1998-08-11 Cirrus Logic, Inc. Fault tolerant sync mark detector for comparing a sign and magnitude of a detected sequence to a target sync mark in sampled amplitude magnetic recording
US5854717A (en) * 1995-09-29 1998-12-29 Seagate Technology, Inc. Self-synchronization in a magnetic recording channel utilizing time-domain equalization
US6101229A (en) * 1996-04-04 2000-08-08 Texas Instruments Incorporated Data synchronization method and circuit using a timeout counter
US5841819A (en) * 1996-04-09 1998-11-24 Thomson Multimedia, S.A. Viterbi decoder for digital packet signals
JPH11251927A (ja) * 1998-03-04 1999-09-17 Sony Corp 情報処理装置および方法、並びに提供媒体

Also Published As

Publication number Publication date
JP2001148169A (ja) 2001-05-29
EP1089486A2 (de) 2001-04-04
EP1089486B1 (de) 2006-11-29
EP1089486A3 (de) 2004-10-27
US6604204B1 (en) 2003-08-05

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Legal Events

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