DE69832674D1 - Phasenregelkreis und Verfahren zur Rückgewinnung eines Taktsignals - Google Patents
Phasenregelkreis und Verfahren zur Rückgewinnung eines TaktsignalsInfo
- Publication number
- DE69832674D1 DE69832674D1 DE69832674T DE69832674T DE69832674D1 DE 69832674 D1 DE69832674 D1 DE 69832674D1 DE 69832674 T DE69832674 T DE 69832674T DE 69832674 T DE69832674 T DE 69832674T DE 69832674 D1 DE69832674 D1 DE 69832674D1
- Authority
- DE
- Germany
- Prior art keywords
- recovering
- phase
- clock signal
- locked loop
- locked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US6034997P | 1997-09-29 | 1997-09-29 | |
US60349P | 1997-09-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69832674D1 true DE69832674D1 (de) | 2006-01-12 |
DE69832674T2 DE69832674T2 (de) | 2006-07-20 |
Family
ID=22028942
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69832674T Expired - Lifetime DE69832674T2 (de) | 1997-09-29 | 1998-09-25 | Phasenregelkreis und Verfahren zur Rückgewinnung eines Taktsignals |
Country Status (3)
Country | Link |
---|---|
US (1) | US6320921B1 (de) |
EP (1) | EP0905909B1 (de) |
DE (1) | DE69832674T2 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2357382B (en) | 1999-12-17 | 2004-03-31 | Mitel Corp | Clock recovery PLL |
US6510526B1 (en) * | 1999-12-23 | 2003-01-21 | Intel Corporation | Differential clocking for digital platforms |
JP3502618B2 (ja) * | 2001-07-19 | 2004-03-02 | 松下電器産業株式会社 | 位相同期ループ回路、及びデータ再生装置 |
US6763294B2 (en) * | 2002-05-06 | 2004-07-13 | Deere & Company | System and method for validating quadrature signals |
US7245682B2 (en) * | 2002-09-30 | 2007-07-17 | Intel Corporation | Determining an optimal sampling clock |
US6970020B1 (en) * | 2003-12-17 | 2005-11-29 | Altera Corporation | Half-rate linear quardrature phase detector for clock recovery |
US8090064B2 (en) * | 2007-02-09 | 2012-01-03 | Fujitsu Limited | Single loop frequency and phase detection |
CN111831965B (zh) * | 2019-04-23 | 2023-09-12 | 千寻位置网络有限公司 | Ssr中upd改正数的完好性监测方法及其装置 |
CN111181552B (zh) * | 2020-01-08 | 2023-03-24 | 电子科技大学 | 一种双向频率同步振荡器电路 |
CN116405058B (zh) * | 2023-06-09 | 2023-09-29 | 中星联华科技(北京)有限公司 | 快速跳频锁定电路及其运行方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69129946T2 (de) * | 1990-05-21 | 1999-04-15 | Nec Corp | Phasenregelkreisschaltung |
US5233314A (en) * | 1992-03-27 | 1993-08-03 | Cyrix Corporation | Integrated charge-pump phase-locked loop circuit |
EP0671829B1 (de) * | 1994-03-11 | 2006-06-28 | Fujitsu Limited | Schaltungsanordnung zur Taktrückgewinnung |
US5740213A (en) * | 1994-06-03 | 1998-04-14 | Dreyer; Stephen F. | Differential charge pump based phase locked loop or delay locked loop |
US5850422A (en) * | 1995-07-21 | 1998-12-15 | Symbios, Inc. | Apparatus and method for recovering a clock signal which is embedded in an incoming data stream |
KR100214503B1 (ko) * | 1996-09-02 | 1999-08-02 | 구본준 | 피에이엠방식 통신장치의 타이밍 복구회로 |
US5870046A (en) * | 1997-04-22 | 1999-02-09 | Silicon Laboratories Inc. | Analog isolation system with digital communication across a capacitive barrier |
US6127865A (en) * | 1997-05-23 | 2000-10-03 | Altera Corporation | Programmable logic device with logic signal delay compensated clock network |
-
1998
- 1998-09-25 US US09/160,905 patent/US6320921B1/en not_active Expired - Lifetime
- 1998-09-25 EP EP98307792A patent/EP0905909B1/de not_active Expired - Lifetime
- 1998-09-25 DE DE69832674T patent/DE69832674T2/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6320921B1 (en) | 2001-11-20 |
EP0905909A3 (de) | 2002-04-03 |
EP0905909A2 (de) | 1999-03-31 |
EP0905909B1 (de) | 2005-12-07 |
DE69832674T2 (de) | 2006-07-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |