DE68912455D1 - Verfahren und Gerät zur Taktsignalsynchronisierung. - Google Patents

Verfahren und Gerät zur Taktsignalsynchronisierung.

Info

Publication number
DE68912455D1
DE68912455D1 DE89307873T DE68912455T DE68912455D1 DE 68912455 D1 DE68912455 D1 DE 68912455D1 DE 89307873 T DE89307873 T DE 89307873T DE 68912455 T DE68912455 T DE 68912455T DE 68912455 D1 DE68912455 D1 DE 68912455D1
Authority
DE
Germany
Prior art keywords
clock signal
signal synchronization
synchronization
clock
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE89307873T
Other languages
English (en)
Other versions
DE68912455T2 (de
Inventor
Neil Frank Dudley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
FFEI Ltd
Original Assignee
Crosfield Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Crosfield Electronics Ltd filed Critical Crosfield Electronics Ltd
Application granted granted Critical
Publication of DE68912455D1 publication Critical patent/DE68912455D1/de
Publication of DE68912455T2 publication Critical patent/DE68912455T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
DE89307873T 1988-08-05 1989-08-02 Verfahren und Gerät zur Taktsignalsynchronisierung. Expired - Fee Related DE68912455T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB888818665A GB8818665D0 (en) 1988-08-05 1988-08-05 Methods & apparatus for synchronising clock signals

Publications (2)

Publication Number Publication Date
DE68912455D1 true DE68912455D1 (de) 1994-03-03
DE68912455T2 DE68912455T2 (de) 1994-05-11

Family

ID=10641677

Family Applications (1)

Application Number Title Priority Date Filing Date
DE89307873T Expired - Fee Related DE68912455T2 (de) 1988-08-05 1989-08-02 Verfahren und Gerät zur Taktsignalsynchronisierung.

Country Status (5)

Country Link
US (1) US4999526A (de)
EP (1) EP0356042B1 (de)
JP (1) JP2930978B2 (de)
DE (1) DE68912455T2 (de)
GB (1) GB8818665D0 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106533399A (zh) * 2015-09-09 2017-03-22 想象技术有限公司 同步装置

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH087558B2 (ja) * 1989-08-30 1996-01-29 日本電気株式会社 走査型表示回路の同期補償回路
US5258660A (en) * 1990-01-16 1993-11-02 Cray Research, Inc. Skew-compensated clock distribution system
US5408640A (en) * 1990-02-21 1995-04-18 Digital Equipment Corporation Phase delay compensator using gating signal generated by a synchronizer for loading and shifting of bit pattern to produce clock phases corresponding to frequency changes
US5124572A (en) * 1990-11-27 1992-06-23 Hewlett-Packard Co. VLSI clocking system using both overlapping and non-overlapping clocks
US5306962A (en) * 1990-11-27 1994-04-26 Hewlett-Packard Company Qualified non-overlapping clock generator to provide control lines with non-overlapping clock timing
US5272390A (en) * 1991-09-23 1993-12-21 Digital Equipment Corporation Method and apparatus for clock skew reduction through absolute delay regulation
US5245637A (en) * 1991-12-30 1993-09-14 International Business Machines Corporation Phase and frequency adjustable digital phase lock logic system
US5452324A (en) * 1992-09-23 1995-09-19 Texas Instruments Incorporated Packet data recovery system
US5467464A (en) * 1993-03-09 1995-11-14 Apple Computer, Inc. Adaptive clock skew and duty cycle compensation for a serial data bus
US5440592A (en) * 1993-03-31 1995-08-08 Intel Corporation Method and apparatus for measuring frequency and high/low time of a digital signal
US5475322A (en) * 1993-10-12 1995-12-12 Wang Laboratories, Inc. Clock frequency multiplying and squaring circuit and method
JPH07154381A (ja) * 1993-11-30 1995-06-16 Hitachi Ltd データ転送装置
US5666079A (en) * 1994-05-06 1997-09-09 Plx Technology, Inc. Binary relative delay line
US5828250A (en) * 1994-09-06 1998-10-27 Intel Corporation Differential delay line clock generator with feedback phase control
US5537068A (en) * 1994-09-06 1996-07-16 Intel Corporation Differential delay line clock generator
US6081147A (en) 1994-09-29 2000-06-27 Fujitsu Limited Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof
US5486783A (en) * 1994-10-31 1996-01-23 At&T Corp. Method and apparatus for providing clock de-skewing on an integrated circuit board
US5506520A (en) * 1995-01-11 1996-04-09 International Business Machines Corporation Energy conserving clock pulse generating circuits
SE504369C2 (sv) 1995-05-02 1997-01-20 Ericsson Telefon Ab L M Fördröjningsanpassad klock- och datagenerator
KR0151261B1 (ko) * 1995-07-14 1998-12-15 문정환 펄스폭 변조 회로
US5805208A (en) * 1995-09-29 1998-09-08 Eastman Kodak Company Positioning system timing synchronization
US5821794A (en) * 1996-04-01 1998-10-13 Cypress Semiconductor Corp. Clock distribution architecture and method for high speed CPLDs
US6272646B1 (en) 1996-09-04 2001-08-07 Cypress Semiconductor Corp. Programmable logic device having an integrated phase lock loop
US5977837A (en) * 1998-05-01 1999-11-02 International Business Machines Corporation Phase selector for external frequency divider and phase locked loop
US6441666B1 (en) 2000-07-20 2002-08-27 Silicon Graphics, Inc. System and method for generating clock signals
US6690224B1 (en) 2001-06-27 2004-02-10 Cypress Semiconductor Corp. Architecture of a PLL with dynamic frequency control on a PLD
KR100871205B1 (ko) * 2002-07-23 2008-12-01 엘지노텔 주식회사 다중 클럭 위상 결정 시스템
DE102006011286B4 (de) * 2006-03-10 2008-02-07 Siemens Ag Österreich Schaltungsanordnung zur Gewinnung synchroner Zeitsignale
US7893772B1 (en) 2007-12-03 2011-02-22 Cypress Semiconductor Corporation System and method of loading a programmable counter
US8990606B2 (en) * 2012-05-15 2015-03-24 Oracle International Corporation Constant frequency architectural timer in a dynamic clock domain
JP2020154230A (ja) * 2019-03-22 2020-09-24 株式会社Ｊｖｃケンウッド 液晶表示装置及びその製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3577128A (en) * 1969-01-14 1971-05-04 Ibm Synchronizing clock system
US3760280A (en) * 1972-06-07 1973-09-18 Taft Broadcasting Corp Method and apparatus for delaying an electrical signal
DE2360450B2 (de) * 1973-12-01 1980-09-04 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Ausfallsicherer Taktgenerator
US4316148A (en) * 1979-09-04 1982-02-16 Sperry Corporation Variable frequency logic clock
US4600895A (en) * 1985-04-26 1986-07-15 Minnesota Mining And Manufacturing Company Precision phase synchronization of free-running oscillator output signal to reference signal
US4851709A (en) * 1987-09-11 1989-07-25 Pacific Northwest Eectronics Variable frequency, fixed amplitude digital sweep generator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106533399A (zh) * 2015-09-09 2017-03-22 想象技术有限公司 同步装置
CN106533399B (zh) * 2015-09-09 2021-10-22 想象技术有限公司 修改时钟信号的电路和方法及执行时间敏感任务的装置

Also Published As

Publication number Publication date
DE68912455T2 (de) 1994-05-11
US4999526A (en) 1991-03-12
EP0356042B1 (de) 1994-01-19
JP2930978B2 (ja) 1999-08-09
EP0356042A1 (de) 1990-02-28
GB8818665D0 (en) 1988-09-07
JPH0276318A (ja) 1990-03-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJIFILM ELECTRONIC IMAGING LTD., LONDON, GB

8339 Ceased/non-payment of the annual fee