DE69410469D1 - Verfahren und Vorrichtung zur Phasenverschiebung eines Taktsignals - Google Patents

Verfahren und Vorrichtung zur Phasenverschiebung eines Taktsignals

Info

Publication number
DE69410469D1
DE69410469D1 DE69410469T DE69410469T DE69410469D1 DE 69410469 D1 DE69410469 D1 DE 69410469D1 DE 69410469 T DE69410469 T DE 69410469T DE 69410469 T DE69410469 T DE 69410469T DE 69410469 D1 DE69410469 D1 DE 69410469D1
Authority
DE
Germany
Prior art keywords
clock signal
phase shifting
shifting
phase
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69410469T
Other languages
English (en)
Other versions
DE69410469T2 (de
Inventor
Roger Maitland
Hal Ireland
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Northern Telecom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northern Telecom Ltd filed Critical Northern Telecom Ltd
Application granted granted Critical
Publication of DE69410469D1 publication Critical patent/DE69410469D1/de
Publication of DE69410469T2 publication Critical patent/DE69410469T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE69410469T 1993-12-09 1994-11-23 Verfahren und Vorrichtung zur Phasenverschiebung eines Taktsignals Expired - Fee Related DE69410469T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/163,643 US5561692A (en) 1993-12-09 1993-12-09 Clock phase shifting method and apparatus
PCT/CA1994/000645 WO1995016307A1 (en) 1993-12-09 1994-11-23 Clock phase shifting method and apparatus

Publications (2)

Publication Number Publication Date
DE69410469D1 true DE69410469D1 (de) 1998-06-25
DE69410469T2 DE69410469T2 (de) 1998-09-17

Family

ID=22590922

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69410469T Expired - Fee Related DE69410469T2 (de) 1993-12-09 1994-11-23 Verfahren und Vorrichtung zur Phasenverschiebung eines Taktsignals

Country Status (5)

Country Link
US (1) US5561692A (de)
EP (1) EP0711472B1 (de)
CA (1) CA2169564C (de)
DE (1) DE69410469T2 (de)
WO (1) WO1995016307A1 (de)

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2719432B1 (fr) * 1994-04-29 1996-07-19 Sgs Thomson Microelectronics Circuit de transmission d'un signal codé en ligne sur une ligne téléphonique.
US6272195B1 (en) * 1995-06-30 2001-08-07 Texas Instruments Incorporated Method and apparatus for correcting signal skew differentials between two interconnected devices
US6115769A (en) * 1996-06-28 2000-09-05 Lsi Logic Corporation Method and apparatus for providing precise circuit delays
US6130566A (en) * 1996-10-30 2000-10-10 Yokomizo; Akira Digital wave shaping circuit, frequency multiplying circuit, and external synchronizing method, and external synchronizing circuit
US5802356A (en) * 1996-11-13 1998-09-01 Integrated Device Technology, Inc. Configurable drive clock
JPH10325887A (ja) * 1997-03-28 1998-12-08 Seiko Instr Inc 論理緩急回路
US6229367B1 (en) * 1997-06-26 2001-05-08 Vitesse Semiconductor Corp. Method and apparatus for generating a time delayed signal with a minimum data dependency error using an oscillator
FR2766275B1 (fr) * 1997-07-21 1999-10-15 Sgs Thomson Microelectronics Circuit de validation de modeles de simulation
US5977805A (en) * 1998-01-21 1999-11-02 Atmel Corporation Frequency synthesis circuit tuned by digital words
US6025744A (en) * 1998-04-17 2000-02-15 International Business Machines Corporation Glitch free delay line multiplexing technique
US6642758B1 (en) 1998-11-03 2003-11-04 Altera Corporation Voltage, temperature, and process independent programmable phase shift for PLL
US6836164B1 (en) 1998-11-03 2004-12-28 Altera Corporation Programmable phase shift circuitry
US6369624B1 (en) * 1998-11-03 2002-04-09 Altera Corporation Programmable phase shift circuitry
US7109765B1 (en) 1998-11-03 2006-09-19 Altera Corporation Programmable phase shift circuitry
US6483886B1 (en) * 1999-01-08 2002-11-19 Altera Corporation Phase-locked loop circuitry for programmable logic devices
US6229344B1 (en) * 1999-03-09 2001-05-08 Vitesse Semiconductor Corp. Phase selection circuit
US6157231A (en) * 1999-03-19 2000-12-05 Credence System Corporation Delay stabilization system for an integrated circuit
US6768356B1 (en) * 2000-09-07 2004-07-27 Iowa State University Research Foundation, Inc. Apparatus for and method of implementing time-interleaved architecture
US6621312B2 (en) 2000-11-13 2003-09-16 Primarion, Inc. High bandwidth multi-phase clock selector with continuous phase output
ATE392632T1 (de) * 2000-11-30 2008-05-15 Geosystems Ag Leica Verfahren und vorrichtung zur frequenzsynthese in einem entfernungsmessgerät
US6737926B2 (en) * 2001-08-30 2004-05-18 Micron Technology, Inc. Method and apparatus for providing clock signals at different locations with minimal clock skew
US6664838B1 (en) * 2001-08-31 2003-12-16 Integrated Device Technology, Inc. Apparatus and method for generating a compensated percent-of-clock period delay signal
JP3995552B2 (ja) * 2002-07-23 2007-10-24 松下電器産業株式会社 クロック逓倍回路
US8340215B2 (en) * 2002-07-26 2012-12-25 Motorola Mobility Llc Radio transceiver architectures and methods
US6856558B1 (en) 2002-09-20 2005-02-15 Integrated Device Technology, Inc. Integrated circuit devices having high precision digital delay lines therein
US7849332B1 (en) 2002-11-14 2010-12-07 Nvidia Corporation Processor voltage adjustment system and method
US7882369B1 (en) 2002-11-14 2011-02-01 Nvidia Corporation Processor performance adjustment system and method
US7886164B1 (en) 2002-11-14 2011-02-08 Nvidia Corporation Processor temperature adjustment system and method
JP4025627B2 (ja) * 2002-11-18 2007-12-26 エルピーダメモリ株式会社 遅延生成方法及びそれに基づく遅延調整方法、並びにそれらを適用した遅延生成回路，遅延調整回路
US7464282B1 (en) 2003-09-03 2008-12-09 T-Ram Semiconductor, Inc. Apparatus and method for producing dummy data and output clock generator using same
US7089439B1 (en) 2003-09-03 2006-08-08 T-Ram, Inc. Architecture and method for output clock generation on a high speed memory device
US6891774B1 (en) 2003-09-03 2005-05-10 T-Ram, Inc. Delay line and output clock generator using same
US6947349B1 (en) 2003-09-03 2005-09-20 T-Ram, Inc. Apparatus and method for producing an output clock pulse and output clock generator using same
TWI223744B (en) * 2003-12-10 2004-11-11 Realtek Semiconductor Corp Method of storage device read phase auto-calibration and related mechanism
US7279938B1 (en) 2004-01-05 2007-10-09 Integrated Device Technology, Inc. Delay chain integrated circuits having binary-weighted delay chain units with built-in phase comparators therein
US7109760B1 (en) 2004-01-05 2006-09-19 Integrated Device Technology, Inc. Delay-locked loop (DLL) integrated circuits that support efficient phase locking of clock signals having non-unity duty cycles
JP2005269147A (ja) * 2004-03-18 2005-09-29 Sanyo Electric Co Ltd 遅延回路
US7342430B1 (en) * 2004-10-05 2008-03-11 Kevin Chiang Write strategy with multi-stage delay cell for providing stable delays on EFM clock
US7739531B1 (en) * 2005-03-04 2010-06-15 Nvidia Corporation Dynamic voltage scaling
TWI309131B (en) * 2005-12-23 2009-04-21 Innolux Display Corp Clock phase adjusting method of monitor
KR100675009B1 (ko) * 2006-02-01 2007-01-29 삼성전자주식회사 데이터 지연 조절 회로 및 방법
US9134782B2 (en) 2007-05-07 2015-09-15 Nvidia Corporation Maintaining optimum voltage supply to match performance of an integrated circuit
DE102007048607B4 (de) 2007-10-10 2019-06-27 Robert Bosch Gmbh Elektronische Schaltung
TWI351198B (en) * 2007-12-26 2011-10-21 Altek Corp Delay apparatus for phase adjustment under smia
US8370663B2 (en) * 2008-02-11 2013-02-05 Nvidia Corporation Power management with dynamic frequency adjustments
US9256265B2 (en) 2009-12-30 2016-02-09 Nvidia Corporation Method and system for artificially and dynamically limiting the framerate of a graphics processing unit
US9830889B2 (en) 2009-12-31 2017-11-28 Nvidia Corporation Methods and system for artifically and dynamically limiting the display resolution of an application
CN102117094A (zh) * 2009-12-31 2011-07-06 张永 芯片速度自适应技术方案
US8839006B2 (en) 2010-05-28 2014-09-16 Nvidia Corporation Power consumption reduction systems and methods
KR101710669B1 (ko) 2010-09-15 2017-02-27 삼성전자주식회사 클록 지연 회로, 지연 동기 회로, 및 그것을 포함하는 반도체 메모리 장치
US8373482B2 (en) * 2011-01-13 2013-02-12 Texas Instruments Incorporated Temperature sensor programmable ring oscillator, processor, and pulse width modulator
US8542049B1 (en) * 2012-04-18 2013-09-24 Texas Instruments Incorporated Methods and delay circuits for generating a plurality of delays in delay lines
US8786340B1 (en) 2013-04-24 2014-07-22 Micron Technology, Inc. Apparatuses, methods, and circuits including a delay circuit having a delay that is adjustable during operation

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4546269A (en) * 1983-12-01 1985-10-08 Control Data Corporation Method and apparatus for optimally tuning clock signals for digital computers
JPS60229521A (ja) * 1984-04-27 1985-11-14 Sony Tektronix Corp デジタル信号遅延回路
US4737670A (en) * 1984-11-09 1988-04-12 Lsi Logic Corporation Delay control circuit
EP0185779B1 (de) * 1984-12-21 1990-02-28 International Business Machines Corporation Digitale Phasenregelschleife
US4821297A (en) * 1987-11-19 1989-04-11 American Telephone And Telegraph Company, At&T Bell Laboratories Digital phase locked loop clock recovery scheme
US4868430A (en) * 1988-02-11 1989-09-19 Ncr Corporation Self-correcting digitally controlled timing circuit
US5018169A (en) * 1989-06-21 1991-05-21 National Semiconductor Corporation High resolution sample clock generator with deglitcher
US5077529A (en) * 1989-07-19 1991-12-31 Level One Communications, Inc. Wide bandwidth digital phase locked loop with reduced low frequency intrinsic jitter
GB2241620B (en) * 1990-02-13 1994-11-30 Matsushita Electric Ind Co Ltd A pulse signal delay device
US5220581A (en) * 1991-03-28 1993-06-15 International Business Machines Corporation Digital data link performance monitor

Also Published As

Publication number Publication date
CA2169564A1 (en) 1995-06-15
DE69410469T2 (de) 1998-09-17
CA2169564C (en) 1999-10-05
EP0711472A1 (de) 1996-05-15
WO1995016307A1 (en) 1995-06-15
US5561692A (en) 1996-10-01
EP0711472B1 (de) 1998-05-20

Similar Documents

Publication Publication Date Title
DE69410469D1 (de) Verfahren und Vorrichtung zur Phasenverschiebung eines Taktsignals
DE69031642D1 (de) Verfahren und Gerät zur Verbesserung eines Multipliziersignals
DE69633039D1 (de) Vorrichtung und Verfahren zur Umwandlung eines Signals
DE69528234D1 (de) Schaltung und Verfahren zur Erzeugung eines Taktsignals
DE69414105D1 (de) Vorrichtung und verfahren zur automatischen erkennung und konfiguration eines peripheriegeräts
DE59308438D1 (de) Verfahren und Vorrichtung zur Feststellung der Funktionsfähigkeit eines Hämo-Dialysators
DE69425400D1 (de) Verfahren und Vorrichtung zur Verschachtelung einer Folge von Datenelementen
DE69516771D1 (de) Vorrichtung und verfahren zur verbesserung der synchronisationserzeugung eines taktsystems
DE69526779D1 (de) Vorrichtung und Verfahren zur Detektion einer angezeigten Position
DE69634656D1 (de) Vorrichtung und Verfahren zur Phasendetektion für ein Lageerfassungssystem
DE69433629D1 (de) Verfahren zur Hestellung eines wärmeleitenden Gerätes und ein wärmeleitendes Gerätes
DE69423557D1 (de) Vorrichtung und Verfahren zur Detektion eines Bewegungsvektors
DE69208345D1 (de) Verfahren und Vorrichtung zur Sicherung eines Gleiskettengelenks
DE69525093D1 (de) Vorrichtung und Verfahren zur Erzeugung eines phasengesteuerten Taktsignals
DE69218460D1 (de) Verfahren und vorrichtung zum erzeugen eines signals
DE69423306D1 (de) Vorrichtung und Verfahren zur Auswahl eines Schriftensatzes
DE69616711D1 (de) Verfahren und Einrichtung zur genauer Frequenzsynthese mit GPS-Taktinformation
DE69425020D1 (de) Verfahren zum Erfassen eines Signales und Gerät zum Erfassen eines Signales
DE69414993D1 (de) Vorrichtung zur Erzeugung eines Anzeigetaktsignals
DE69432092D1 (de) Vorrichtung und Verfahren zur Veränderung des Massstabs eines gedruckten Musters
DE69534298D1 (de) Verfahren und Vorrichtung zur Ermittlung einer Phasendifferenz und Filterschaltung
DE69404311D1 (de) Verfahren und vorrichtung zur festphasenextraktion
DE69327612D1 (de) Schaltung und Verfahren zur Generierung eines stabilen Taktsignals mit Frequenzvervielfachung
DE69332302D1 (de) Verfahren und Vorrichtung zur adaptiver Umsetzung in ein Zeilenfolgesignal
DE69612958D1 (de) Verfahren und vorrichtung zur resynthetisierung eines sprachsignals

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee