DE69918250D1 - Vorrichtung zur Wiedergewinnung und Identifizierung eines Taktsignals - Google Patents
Vorrichtung zur Wiedergewinnung und Identifizierung eines TaktsignalsInfo
- Publication number
- DE69918250D1 DE69918250D1 DE69918250T DE69918250T DE69918250D1 DE 69918250 D1 DE69918250 D1 DE 69918250D1 DE 69918250 T DE69918250 T DE 69918250T DE 69918250 T DE69918250 T DE 69918250T DE 69918250 D1 DE69918250 D1 DE 69918250D1
- Authority
- DE
- Germany
- Prior art keywords
- recovering
- identifying
- clock signal
- clock
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34379098 | 1998-12-03 | ||
| JP34379098 | 1998-12-03 | ||
| JP12121499A JP3931477B2 (ja) | 1998-12-03 | 1999-04-28 | クロック再生/識別装置 |
| JP12121499 | 1999-04-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69918250D1 true DE69918250D1 (de) | 2004-07-29 |
| DE69918250T2 DE69918250T2 (de) | 2005-07-21 |
Family
ID=26458627
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69918250T Expired - Lifetime DE69918250T2 (de) | 1998-12-03 | 1999-10-11 | Vorrichtung zur Wiedergewinnung und Identifizierung eines Taktsignals |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6249160B1 (de) |
| EP (1) | EP1006660B1 (de) |
| JP (1) | JP3931477B2 (de) |
| DE (1) | DE69918250T2 (de) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7454644B2 (en) * | 2001-06-15 | 2008-11-18 | Stmicroelectronics Sa | Integrated circuit with low current consumption having a one wire communication interface |
| JP3866959B2 (ja) | 2001-11-07 | 2007-01-10 | 三菱電機株式会社 | 周波数差検知装置および周波数差検知方法 |
| JP4093826B2 (ja) * | 2002-08-27 | 2008-06-04 | 富士通株式会社 | クロック発生装置 |
| JP4586730B2 (ja) | 2003-12-08 | 2010-11-24 | 日本電気株式会社 | クロックデータ再生回路 |
| FR2914808B1 (fr) * | 2007-04-06 | 2009-06-05 | Cnes Epic | Dispositif d'extraction d'horloge et de donnees numeriques sans reglage externe |
| KR101847543B1 (ko) * | 2011-10-05 | 2018-05-24 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그의 동작 방법 |
| DE102014210521A1 (de) * | 2014-06-03 | 2015-12-03 | Continental Teves Ag & Co. Ohg | Jitterkompensation im Taktgenerator eines Drehratensensors |
| US9130807B1 (en) * | 2014-07-01 | 2015-09-08 | Xilinx, Inc. | Data recovery unit (DRU) based on free running oversampling with zero-latency loop |
| JP6604859B2 (ja) * | 2016-01-21 | 2019-11-13 | ザインエレクトロニクス株式会社 | クロック生成装置およびクロックデータ復元装置 |
| CN115001486A (zh) * | 2021-03-01 | 2022-09-02 | 中兴通讯股份有限公司 | 时钟数据恢复电路及时钟数据恢复方法 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4320515A (en) * | 1980-03-07 | 1982-03-16 | Harris Corporation | Bit synchronizer |
| US4309673A (en) * | 1980-03-10 | 1982-01-05 | Control Data Corporation | Delay lock loop modulator and demodulator |
| US4339823A (en) * | 1980-08-15 | 1982-07-13 | Motorola, Inc. | Phase corrected clock signal recovery circuit |
| US4949051A (en) * | 1989-09-01 | 1990-08-14 | General Electric Company | Phase lock clock recovery with aided frequency aquisition |
| US5124669A (en) * | 1990-09-18 | 1992-06-23 | Silicon Systems, Inc. | One-shot circuit for use in a PLL clock recovery circuit |
| US5164966A (en) * | 1991-03-07 | 1992-11-17 | The Grass Valley Group, Inc. | Nrz clock and data recovery system employing phase lock loop |
| US5488641A (en) * | 1992-12-10 | 1996-01-30 | Northern Telecom Limited | Digital phase-locked loop circuit |
| KR950011625B1 (ko) * | 1993-12-14 | 1995-10-06 | 재단법인한국전자통신연구소 | 데이타 및 클럭 복원회로 |
| JPH0946197A (ja) * | 1995-07-28 | 1997-02-14 | Ando Electric Co Ltd | 可変遅延回路 |
| US5671259A (en) * | 1995-08-24 | 1997-09-23 | Northern Telecom Limited | Clock recovery circuit |
-
1999
- 1999-04-28 JP JP12121499A patent/JP3931477B2/ja not_active Expired - Fee Related
- 1999-08-18 US US09/376,496 patent/US6249160B1/en not_active Expired - Fee Related
- 1999-10-11 EP EP99120278A patent/EP1006660B1/de not_active Expired - Lifetime
- 1999-10-11 DE DE69918250T patent/DE69918250T2/de not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000228660A (ja) | 2000-08-15 |
| JP3931477B2 (ja) | 2007-06-13 |
| DE69918250T2 (de) | 2005-07-21 |
| US6249160B1 (en) | 2001-06-19 |
| EP1006660A2 (de) | 2000-06-07 |
| EP1006660A3 (de) | 2002-12-04 |
| EP1006660B1 (de) | 2004-06-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition |