DE69812122D1 - Verfahren und schaltung zur kalibrierung paralleller analog-digital-wandler - Google Patents

Verfahren und schaltung zur kalibrierung paralleller analog-digital-wandler

Info

Publication number
DE69812122D1
DE69812122D1 DE69812122T DE69812122T DE69812122D1 DE 69812122 D1 DE69812122 D1 DE 69812122D1 DE 69812122 T DE69812122 T DE 69812122T DE 69812122 T DE69812122 T DE 69812122T DE 69812122 D1 DE69812122 D1 DE 69812122D1
Authority
DE
Germany
Prior art keywords
circuit
digital converter
parallel analog
calibrating parallel
calibrating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69812122T
Other languages
English (en)
Inventor
Russel Croman
P Hein
Maurius Goldenberg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cirrus Logic Inc
Original Assignee
Cirrus Logic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cirrus Logic Inc filed Critical Cirrus Logic Inc
Application granted granted Critical
Publication of DE69812122D1 publication Critical patent/DE69812122D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/1023—Offset correction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
    • H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Manipulation Of Pulses (AREA)
DE69812122T 1997-09-05 1998-08-14 Verfahren und schaltung zur kalibrierung paralleller analog-digital-wandler Expired - Lifetime DE69812122D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/924,108 US5990814A (en) 1997-09-05 1997-09-05 Method and circuit for calibration of flash analog to digital converters
PCT/US1998/016898 WO1999013583A1 (en) 1997-09-05 1998-08-14 Method and circuit for calibration of flash analog to digital converters

Publications (1)

Publication Number Publication Date
DE69812122D1 true DE69812122D1 (de) 2003-04-17

Family

ID=25449718

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69812122T Expired - Lifetime DE69812122D1 (de) 1997-09-05 1998-08-14 Verfahren und schaltung zur kalibrierung paralleller analog-digital-wandler

Country Status (7)

Country Link
US (1) US5990814A (de)
EP (1) EP1010252B1 (de)
JP (1) JP2001516982A (de)
KR (1) KR20010023643A (de)
AU (1) AU8907198A (de)
DE (1) DE69812122D1 (de)
WO (1) WO1999013583A1 (de)

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US6690311B2 (en) 1998-11-20 2004-02-10 Telefonaktiebolaget Lm Ericsson (Publ) Adaptively calibrating analog-to-digital conversion with correction table indexing
US6127955A (en) * 1998-11-20 2000-10-03 Telefonaktiebolaget Lm Ericsson (Publ) Method and system for calibrating analog-to-digital conversion
US6445317B2 (en) * 1998-11-20 2002-09-03 Telefonaktiebolaget L M Ericsson (Publ) Adaptively calibrating analog-to-digital conversion
US6255979B1 (en) * 1999-02-24 2001-07-03 Intel Corporation CMOS flash analog to digital converter compensation
US6288667B1 (en) * 2000-03-13 2001-09-11 Massachusetts Institute Of Technology Low power analog-to-digital converter
US6420983B1 (en) * 2000-05-25 2002-07-16 Texas Instruments Incorporated On-line offset cancellation in flash A/D with interpolating comparator array
US6504499B1 (en) * 2000-11-01 2003-01-07 International Business Machines Corporation Analog-to-digital converter having positively biased differential reference inputs
SE520277C2 (sv) * 2001-02-27 2003-06-17 Ericsson Telefon Ab L M Införande av kalibreringssekvens hos en A/D-omvandlare
US6459394B1 (en) 2001-05-22 2002-10-01 Cirrus Logic, Inc. Multi-bank flash ADC array with uninterrupted operation during offset calibration and auto-zero
TW564598B (en) * 2001-07-13 2003-12-01 Via Tech Inc Data converter using active interpolation in background auto-zeroing
US6396430B1 (en) * 2001-08-14 2002-05-28 Texas Instruments Incorporated Pre-amplifier design for high-speed analog-to-digital converters
JP3709846B2 (ja) * 2002-01-18 2005-10-26 ソニー株式会社 並列型ａｄ変換器
SE521575C2 (sv) * 2002-03-25 2003-11-11 Ericsson Telefon Ab L M Kalibrering av A/D omvandlare
US6856265B2 (en) * 2002-03-28 2005-02-15 Via Technologies Inc. Data converter with background auto-zeroing via active interpolation
US6816096B2 (en) * 2002-04-23 2004-11-09 Ultra Design, L.L.C. Response-based analog-to-digital conversion apparatus and method
US7231306B1 (en) * 2002-04-30 2007-06-12 Rambus Inc. Method and apparatus for calibrating static timing offsets across multiple outputs
DE10239859B3 (de) * 2002-08-29 2004-04-15 Advanced Micro Devices, Inc., Sunnyvale Vorrichtung und Verfahren zur Spannungsspitzen-Messung mit digitalem Speicher
US6980139B2 (en) * 2002-08-29 2005-12-27 Infineon Technologies Ag Sigma-delta-modulator
EP1394950B1 (de) * 2002-08-29 2006-08-02 Infineon Technologies AG Quantisierer für einen Sigma-Delta-Modulator und Sigma-Delta-Modulator
US7397848B2 (en) 2003-04-09 2008-07-08 Rambus Inc. Partial response receiver
US6927713B2 (en) * 2003-04-23 2005-08-09 Ultradesign, Llc Response-based analog-to-digital conversion apparatus and method
US6833800B1 (en) 2003-09-17 2004-12-21 Analog Devices, Inc. Differential comparator systems with enhanced dynamic range
US7218258B2 (en) * 2004-02-05 2007-05-15 Broadcom Corporation Method and system for mixed analog-digital automatic gain control
US7106230B2 (en) * 2004-06-17 2006-09-12 Kenet, Inc. Analog to digital converter calibration via synchronous demodulation
US7245244B1 (en) 2004-08-03 2007-07-17 Analog Devices, Inc. Correction methods and structures for analog-to-digital converter transfer functions
US7161523B1 (en) 2004-09-03 2007-01-09 Pmc-Sierra, Inc. Systems and methods for a self-organizing analog-to-digital converter
US7233274B1 (en) * 2005-12-20 2007-06-19 Impinj, Inc. Capacitive level shifting for analog signal processing
US7352307B2 (en) * 2006-02-09 2008-04-01 Atmel Corporation Comparator chain offset reduction
EP1921749B1 (de) * 2006-11-13 2010-08-04 Rohde & Schwarz GmbH & Co. KG Schaltung und Verfahren zum Erzeugen einer Reihe von Zwischenspannungen
JP4469902B2 (ja) * 2008-03-04 2010-06-02 富士通株式会社 半導体装置及びその制御方法
US7813199B2 (en) * 2008-04-22 2010-10-12 Micron Technology, Inc. Current mode data sensing and propagation using voltage amplifier
US7492301B1 (en) * 2008-07-29 2009-02-17 International Business Machines Corporation Low power to analog to digital converter with small input capacitance
JP2010124449A (ja) * 2008-10-21 2010-06-03 Renesas Electronics Corp アナログデジタル変換回路
JP2010268349A (ja) * 2009-05-18 2010-11-25 Renesas Electronics Corp アナログ／デジタル変換回路及びアナログ／デジタル変換方法
US7936298B2 (en) * 2009-09-18 2011-05-03 Mediatek Singapore Pte. Ltd. Integrated circuit and electronic device comprising threshold generation circuitry and method therefor
US8350737B2 (en) 2011-01-12 2013-01-08 International Business Machines Corporation Flash analog to digital converter with method and system for dynamic calibration
US8416106B2 (en) * 2011-04-20 2013-04-09 Fujitsu Limited Calibration scheme for resolution scaling, power scaling, variable input swing and comparator offset cancellation for flash ADCs
US8901937B2 (en) * 2011-10-18 2014-12-02 Analog Devices, Inc. Foreground techniques for comparator calibration
US9143371B1 (en) * 2013-07-15 2015-09-22 Pmc-Sierra Us, Inc. Method for reducing jitter in receivers
RU2544783C1 (ru) * 2014-03-27 2015-03-20 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Уфимский государственный авиационный технический университет" Управляемое прецизионное регенеративное пороговое устройство
DE102015212848A1 (de) * 2015-07-09 2017-01-12 Forschungszentrum Jülich GmbH Filterschaltung zur Filterung eines Eingangssignals eines Analog-Digital-Wandlers
TWI657666B (zh) * 2017-10-31 2019-04-21 聯陽半導體股份有限公司 類比至數位轉換器及其校正方法以及校正設備
US10866277B2 (en) * 2018-08-30 2020-12-15 Nxp B.V. Analog-test-bus apparatuses involving calibration of comparator circuits and methods thereof
US11005469B1 (en) * 2019-11-27 2021-05-11 Robert Bosch Gmbh Two step high speed auto-zero and self-calibration comparator

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JPS6011849B2 (ja) * 1976-02-10 1985-03-28 日本電気株式会社 オフセツト補償回路
FR2396463A1 (fr) * 1977-06-30 1979-01-26 Ibm France Circuit pour compenser les decalages du zero dans les dispositifs analogiques et application de ce circuit a un convertisseur analogique-numerique
JPS5728517U (de) * 1980-07-22 1982-02-15
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US4799041A (en) * 1986-10-06 1989-01-17 Applied Automation, Inc. Recirculating analog to digital converter with auto-calibrating feature
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US5335365A (en) * 1991-07-08 1994-08-02 Motorola, Inc. Frequency synthesizer with VCO output control
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JP3222276B2 (ja) * 1993-07-30 2001-10-22 セイコーインスツルメンツ株式会社 コンパレータ回路およびコンパレータ回路の制御方法
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Also Published As

Publication number Publication date
AU8907198A (en) 1999-03-29
KR20010023643A (ko) 2001-03-26
WO1999013583A1 (en) 1999-03-18
EP1010252A1 (de) 2000-06-21
JP2001516982A (ja) 2001-10-02
US5990814A (en) 1999-11-23
EP1010252B1 (de) 2003-03-12

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: CIRRUS LOGIC, INC., AUSTIN, TEX., US

8332 No legal effect for de