FR2396463A1 - Circuit pour compenser les decalages du zero dans les dispositifs analogiques et application de ce circuit a un convertisseur analogique-numerique - Google Patents

Circuit pour compenser les decalages du zero dans les dispositifs analogiques et application de ce circuit a un convertisseur analogique-numerique

Info

Publication number
FR2396463A1
FR2396463A1 FR7720730A FR7720730A FR2396463A1 FR 2396463 A1 FR2396463 A1 FR 2396463A1 FR 7720730 A FR7720730 A FR 7720730A FR 7720730 A FR7720730 A FR 7720730A FR 2396463 A1 FR2396463 A1 FR 2396463A1
Authority
FR
France
Prior art keywords
circuit
analogue
application
sign
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7720730A
Other languages
English (en)
Other versions
FR2396463B1 (fr
Inventor
Pierre Debord
Jean-Louis Marijon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compagnie IBM France SAS
Original Assignee
Compagnie IBM France SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compagnie IBM France SAS filed Critical Compagnie IBM France SAS
Priority to FR7720730A priority Critical patent/FR2396463A1/fr
Priority to GB16559/78A priority patent/GB1599572A/en
Priority to JP53061810A priority patent/JPS5919488B2/ja
Priority to DE19782823214 priority patent/DE2823214A1/de
Priority to US05/912,123 priority patent/US4251803A/en
Publication of FR2396463A1 publication Critical patent/FR2396463A1/fr
Application granted granted Critical
Publication of FR2396463B1 publication Critical patent/FR2396463B1/fr
Priority to US06/139,329 priority patent/US4380005A/en
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/303—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters using a switching device
    • H03F1/304—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters using a switching device and using digital means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/129—Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling ; Out-of-range indication
    • H03M1/1295—Clamping, i.e. adjusting the DC level of the input signal to a predetermined value

Abstract

Circuit pour compenser les décalages du zéro introduits par les dispositifs analogiques traitant des signaux de valeurs moyennes nulles. Ce circuit comprend des moyens pour indiquer le signe du signal de sortie par rapport au zéro décalé et deux sources de courants 42 et 41 fournissant des courants 21 et 1 à un point M. Le point M est connecté à une capacité 45. Si le signe du signal de sortie est positif, le transistor 47 est rendu con ucteur ainsi que la diode 46 et la capacité est déchargée par un courant -I. Si le signe est négatif, les deux sources débitent et la capacité est chargée par un courant I. La tension au point M est la tension de compensation ajoutée au signal d'entrée. Application aux convertisseurs analogique-numérique.
FR7720730A 1977-06-30 1977-06-30 Circuit pour compenser les decalages du zero dans les dispositifs analogiques et application de ce circuit a un convertisseur analogique-numerique Granted FR2396463A1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
FR7720730A FR2396463A1 (fr) 1977-06-30 1977-06-30 Circuit pour compenser les decalages du zero dans les dispositifs analogiques et application de ce circuit a un convertisseur analogique-numerique
GB16559/78A GB1599572A (en) 1977-06-30 1978-04-26 Circuit for compensating zero offsets in analogue devices
JP53061810A JPS5919488B2 (ja) 1977-06-30 1978-05-25 零オフセツト補償装置
DE19782823214 DE2823214A1 (de) 1977-06-30 1978-05-27 Schaltungsanordnung zur kompensierung des nullversatzes des ausgangssignals einer ein analogsignal verarbeitenden uebergeordneten anordnung
US05/912,123 US4251803A (en) 1977-06-30 1978-06-02 Dynamic zero offset compensating circuit for A/D converter
US06/139,329 US4380005A (en) 1977-06-30 1980-04-11 Dynamic zero offset compensating circuit for A/D converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7720730A FR2396463A1 (fr) 1977-06-30 1977-06-30 Circuit pour compenser les decalages du zero dans les dispositifs analogiques et application de ce circuit a un convertisseur analogique-numerique

Publications (2)

Publication Number Publication Date
FR2396463A1 true FR2396463A1 (fr) 1979-01-26
FR2396463B1 FR2396463B1 (fr) 1980-02-08

Family

ID=9193035

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7720730A Granted FR2396463A1 (fr) 1977-06-30 1977-06-30 Circuit pour compenser les decalages du zero dans les dispositifs analogiques et application de ce circuit a un convertisseur analogique-numerique

Country Status (5)

Country Link
US (2) US4251803A (fr)
JP (1) JPS5919488B2 (fr)
DE (1) DE2823214A1 (fr)
FR (1) FR2396463A1 (fr)
GB (1) GB1599572A (fr)

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FR2599913A1 (fr) * 1986-06-07 1987-12-11 Sony Corp Circuit convertisseur analogique/numerique bipolaire a compensation de decalage automatique
EP0331850A2 (fr) * 1988-03-09 1989-09-13 Nortel Networks Corporation Dispositif et procédé de conversion analogique-numérique à gain variable
EP0589749A1 (fr) * 1992-09-25 1994-03-30 Thomson-Csf Circuit de codage analogique-numérique à compensation automatique du décalage du zéro

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DE3031592A1 (de) * 1980-08-21 1982-03-18 Siemens AG, 1000 Berlin und 8000 München Verfahren zum nullpunktabgleich des durch einen operationsverstaerker realisierten analogwertvergleichers eines unter verwendung eines digital-analog-wandlers nach dem iterativprinzip arbeitenden analog-digital-wandlers, insbesondere bei dessen zugehoerigkeit zu einer einrichtung zur analog-digital-wandlung und umgekehrt zur digital-analog-wandlung (codec)
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DE3126380A1 (de) * 1981-07-03 1983-01-20 Texas Instruments Deutschland Gmbh, 8050 Freising "schaltungsanordnung zum umsetzen eines analogen wechselspannungssignals in ein digitales signal"
US5610810A (en) * 1981-09-06 1997-03-11 Canon Kabushiki Kaisha Apparatus for correcting errors in a digital-to-analog converter
US4486707A (en) * 1982-09-24 1984-12-04 Sangamo Weston, Inc. Gain switching device with reduced error for watt meter
JPS5953539U (ja) * 1982-09-30 1984-04-07 日本ビクター株式会社 表示装置
EP0112428B1 (fr) * 1982-12-28 1987-08-12 International Business Machines Corporation Convertisseur analogique/numérique
JPS59137644U (ja) * 1983-03-07 1984-09-13 ナカミチ株式会社 蓄積型ｄ／ａ変換器
JPS6029025A (ja) * 1983-07-14 1985-02-14 Toshiba Corp Ａ−ｄ変換器のオフセット・ドリフト補正回路
US4710889A (en) * 1983-07-25 1987-12-01 Cain Encoder Co. Angular position detector
US4616329A (en) * 1983-08-26 1986-10-07 Bio-Rad Laboratories, Inc. Self-calibrating adaptive ranging apparatus and method
JPS6110034A (ja) * 1984-06-25 1986-01-17 Olympus Optical Co Ltd ガラスプレスレンズの成形装置
DE3432091A1 (de) * 1984-08-28 1986-03-13 Hahn-Meitner-Institut für Kernforschung Berlin GmbH, 1000 Berlin Schaltungsanordnung fuer ein messgeraet mit automatischem nullinienabgleich
US4590458A (en) * 1985-03-04 1986-05-20 Exxon Production Research Co. Offset removal in an analog to digital conversion system
IT1186477B (it) * 1985-12-19 1987-11-26 Sgs Microelettronica Spa Metodo ed apparecchio per piastrina di combinazione per modulazione di codile di impulso avente un perfezionato circuito di autoazzeramento
FR2599852B1 (fr) * 1986-06-06 1988-06-24 Labo Electronique Physique Circuit d'entree pour sonde d'analyseur logique, et sonde et analyseur logique munis d'un tel circuit
GB2199710A (en) * 1986-12-23 1988-07-13 Philips Electronic Associated Analogue to digital converter
US4965867A (en) * 1987-08-20 1990-10-23 Pioneer Electronic Corporation Offset compensation circuit
US5034746A (en) * 1988-09-21 1991-07-23 International Business Machines Corporation Analog-to-digital converter for computer disk file servo position error signal
US4942399A (en) * 1989-03-15 1990-07-17 International Business Machines Corporation Adaptive flash analog/digital converter for differential input signal
US5245340A (en) * 1989-06-27 1993-09-14 Her Majesty The Queen In Right Of Canada, As Represented By The Minister Of Communications Digital transmultiplexer with automatic threshold controller
JP2924373B2 (ja) * 1990-11-02 1999-07-26 日本電気株式会社 Ａ／ｄ変換回路
US5515050A (en) * 1993-07-06 1996-05-07 Advanced Micro Devices, Inc. Apparatus and method for asynchronous successive approximation
US5523756A (en) * 1994-01-18 1996-06-04 The Grass Valley Group, Inc. Analog-to-digital converter with offset reduction loop
AT403229B (de) * 1994-02-10 1997-12-29 Semcotec Handel Schaltungsanordnung
KR960009110U (ko) * 1994-08-12 1996-03-16 오디오 시스템의 직류 오프셋 보상회로
JPH1011899A (ja) * 1996-06-27 1998-01-16 Canon Inc デジタル信号処理装置
FR2755323A1 (fr) * 1996-10-25 1998-04-30 Philips Electronics Nv Dispositif de conversion analogique/numerique
US5990707A (en) * 1997-09-05 1999-11-23 Cirrus Logic, Inc. Method and system for sliced integration of flash analog to digital converters in read channel circuits
US5990814A (en) * 1997-09-05 1999-11-23 Cirrus Logic, Inc. Method and circuit for calibration of flash analog to digital converters
JP2980576B2 (ja) * 1997-09-12 1999-11-22 株式会社東芝 物理乱数発生装置及び方法並びに物理乱数記録媒体
FR2798526B1 (fr) * 1999-09-15 2001-11-09 Schneider Electric Ind Sa Declencheur electronique avec des moyens de correction d'offset
US6625232B1 (en) * 2000-05-22 2003-09-23 Motorola, Inc. Smart DC offset correction loop
EP1258981A1 (fr) 2001-05-18 2002-11-20 Alcatel Montage amplificateur opérationnel avec un circuit de commande du courant de repos
DE60131375T2 (de) * 2001-05-18 2008-10-16 Alcatel Lucent Operationsverstärkeranordnung mit Ruhestromeinstellungschaltung
US6975682B2 (en) * 2001-06-12 2005-12-13 Raytheon Company Multi-bit delta-sigma analog-to-digital converter with error shaping
US7049855B2 (en) * 2001-06-28 2006-05-23 Intel Corporation Area efficient waveform evaluation and DC offset cancellation circuits
JP2005532731A (ja) * 2002-07-05 2005-10-27 レイセオン・カンパニー エラー成形手段を有する多ビットデルタ・シグマアナログ・デジタル変換器
US6980139B2 (en) * 2002-08-29 2005-12-27 Infineon Technologies Ag Sigma-delta-modulator
DE50207726D1 (de) * 2002-08-29 2006-09-14 Infineon Technologies Ag Quantisierer für einen Sigma-Delta-Modulator und Sigma-Delta-Modulator
DE60307226D1 (de) * 2003-02-18 2006-09-14 St Microelectronics Srl Analog-Digital-Wandler mit Korrektur von Verschiebungsfehlern
US7242330B2 (en) * 2003-12-17 2007-07-10 Texas Instruments Incorporated Dynamic compensation of analog-to-digital converter (ADC) offset errors using filtered PWM
CN100542040C (zh) * 2004-12-06 2009-09-16 凌阳科技股份有限公司 零位准误差自动补偿电路与方法
US7233274B1 (en) * 2005-12-20 2007-06-19 Impinj, Inc. Capacitive level shifting for analog signal processing
US7352307B2 (en) * 2006-02-09 2008-04-01 Atmel Corporation Comparator chain offset reduction
US7746119B2 (en) * 2008-09-18 2010-06-29 Power Integrations, Inc. Leakage compensation for sample and hold devices
JP5223715B2 (ja) * 2009-02-13 2013-06-26 富士通株式会社 レベル判定装置の判定方法
US8779952B1 (en) * 2012-04-12 2014-07-15 Pmc-Sierra Us, Inc. Background calibration of threshold errors in analog to digital converters
US8810442B1 (en) 2013-02-14 2014-08-19 Pmc-Sierra Us, Inc. Background calibration of aperture center errors in analog to digital converters

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2599913A1 (fr) * 1986-06-07 1987-12-11 Sony Corp Circuit convertisseur analogique/numerique bipolaire a compensation de decalage automatique
EP0331850A2 (fr) * 1988-03-09 1989-09-13 Nortel Networks Corporation Dispositif et procédé de conversion analogique-numérique à gain variable
EP0331850A3 (fr) * 1988-03-09 1991-08-14 Nortel Networks Corporation Dispositif et procédé de conversion analogique-numérique à gain variable
EP0589749A1 (fr) * 1992-09-25 1994-03-30 Thomson-Csf Circuit de codage analogique-numérique à compensation automatique du décalage du zéro
FR2696300A1 (fr) * 1992-09-25 1994-04-01 Thomson Csf Circuit de codage analogique-numérique à compensation automatique du décalage du zéro.
US5424738A (en) * 1992-09-25 1995-06-13 Thomson-Csf Analog-digital encoding circuit with automatic compensation for the zero offset

Also Published As

Publication number Publication date
GB1599572A (en) 1981-10-07
JPS5413247A (en) 1979-01-31
DE2823214A1 (de) 1979-01-04
JPS5919488B2 (ja) 1984-05-07
US4251803A (en) 1981-02-17
US4380005A (en) 1983-04-12
FR2396463B1 (fr) 1980-02-08

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