DE69728805T2 - Integrierte Schaltung mit Gate-Array-Verbindungen, die über das Speichergebiet geführt werden - Google Patents

Integrierte Schaltung mit Gate-Array-Verbindungen, die über das Speichergebiet geführt werden Download PDF

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Publication number
DE69728805T2
DE69728805T2 DE69728805T DE69728805T DE69728805T2 DE 69728805 T2 DE69728805 T2 DE 69728805T2 DE 69728805 T DE69728805 T DE 69728805T DE 69728805 T DE69728805 T DE 69728805T DE 69728805 T2 DE69728805 T2 DE 69728805T2
Authority
DE
Germany
Prior art keywords
integrated circuit
storage area
gate array
connections routed
array connections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69728805T
Other languages
English (en)
Other versions
DE69728805D1 (de
Inventor
Noriaki Shinagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of DE69728805D1 publication Critical patent/DE69728805D1/de
Application granted granted Critical
Publication of DE69728805T2 publication Critical patent/DE69728805T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225—Shielding layers formed together with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
DE69728805T 1996-02-22 1997-02-13 Integrierte Schaltung mit Gate-Array-Verbindungen, die über das Speichergebiet geführt werden Expired - Fee Related DE69728805T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8034635A JPH09232435A (ja) 1996-02-22 1996-02-22 半導体集積回路

Publications (2)

Publication Number Publication Date
DE69728805D1 DE69728805D1 (de) 2004-06-03
DE69728805T2 true DE69728805T2 (de) 2005-04-21

Family

ID=12419876

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69728805T Expired - Fee Related DE69728805T2 (de) 1996-02-22 1997-02-13 Integrierte Schaltung mit Gate-Array-Verbindungen, die über das Speichergebiet geführt werden

Country Status (7)

Country Link
US (1) US5886371A (de)
EP (1) EP0791963B1 (de)
JP (1) JPH09232435A (de)
KR (1) KR100336155B1 (de)
CN (1) CN1085410C (de)
DE (1) DE69728805T2 (de)
TW (1) TW354420B (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6786420B1 (en) 1997-07-15 2004-09-07 Silverbrook Research Pty. Ltd. Data distribution mechanism in the form of ink dots on cards
TW399319B (en) * 1997-03-19 2000-07-21 Hitachi Ltd Semiconductor device
US6547364B2 (en) * 1997-07-12 2003-04-15 Silverbrook Research Pty Ltd Printing cartridge with an integrated circuit device
US6618117B2 (en) 1997-07-12 2003-09-09 Silverbrook Research Pty Ltd Image sensing apparatus including a microcontroller
US6624848B1 (en) 1997-07-15 2003-09-23 Silverbrook Research Pty Ltd Cascading image modification using multiple digital cameras incorporating image processing
US6690419B1 (en) 1997-07-15 2004-02-10 Silverbrook Research Pty Ltd Utilising eye detection methods for image processing in a digital image camera
AUPO802797A0 (en) 1997-07-15 1997-08-07 Silverbrook Research Pty Ltd Image processing method and apparatus (ART54)
AUPO850597A0 (en) 1997-08-11 1997-09-04 Silverbrook Research Pty Ltd Image processing method and apparatus (art01a)
US6948794B2 (en) 1997-07-15 2005-09-27 Silverbrook Reserach Pty Ltd Printhead re-capping assembly for a print and demand digital camera system
US6879341B1 (en) 1997-07-15 2005-04-12 Silverbrook Research Pty Ltd Digital camera system containing a VLIW vector processor
US6985207B2 (en) 1997-07-15 2006-01-10 Silverbrook Research Pty Ltd Photographic prints having magnetically recordable media
US7110024B1 (en) 1997-07-15 2006-09-19 Silverbrook Research Pty Ltd Digital camera system having motion deblurring means
US6166403A (en) * 1997-11-12 2000-12-26 Lsi Logic Corporation Integrated circuit having embedded memory with electromagnetic shield
AUPP702098A0 (en) 1998-11-09 1998-12-03 Silverbrook Research Pty Ltd Image creation method and apparatus (ART73)
AUPQ056099A0 (en) 1999-05-25 1999-06-17 Silverbrook Research Pty Ltd A method and apparatus (pprint01)
US6492736B1 (en) * 2001-03-14 2002-12-10 Lsi Logic Corporation Power mesh bridge
JP2003273231A (ja) * 2002-03-19 2003-09-26 Fujitsu Ltd 半導体集積回路のシールド構造
JP2004031389A (ja) * 2002-06-21 2004-01-29 Fujitsu Ltd 半導体回路設計方法、半導体回路設計装置、プログラム及び半導体装置
JP4521611B2 (ja) * 2004-04-09 2010-08-11 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
JP5571547B2 (ja) * 2007-04-09 2014-08-13 プレジデント アンド フェローズ オブ ハーバード カレッジ 銅の相互接続体のための窒化コバルト層及びそれらを形成する方法
US8530880B2 (en) * 2009-07-27 2013-09-10 Hewlett-Packard Development Company, L.P. Reconfigurable multilayer circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6197849A (ja) * 1984-10-18 1986-05-16 Fujitsu Ltd ゲ−トアレイｌｓｉ装置
KR920005863B1 (ko) * 1988-08-12 1992-07-23 산요덴끼 가부시끼가이샤 반도체 집적회로
JPH02106968A (ja) * 1988-10-17 1990-04-19 Hitachi Ltd 半導体集積回路装置及びその形成方法
US5321280A (en) * 1990-09-13 1994-06-14 Nec Corporation Composite semiconductor integrated circuit device

Also Published As

Publication number Publication date
EP0791963B1 (de) 2004-04-28
TW354420B (en) 1999-03-11
US5886371A (en) 1999-03-23
KR970063679A (ko) 1997-09-12
JPH09232435A (ja) 1997-09-05
CN1169035A (zh) 1997-12-31
DE69728805D1 (de) 2004-06-03
CN1085410C (zh) 2002-05-22
EP0791963A1 (de) 1997-08-27
KR100336155B1 (ko) 2002-09-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: PUSCHMANN & BORCHERT, 82041 OBERHACHING

8339 Ceased/non-payment of the annual fee