DE69721361D1 - Einchipspeichersystem mit einem Dekoder für Pulswortleitungsverfahren - Google Patents

Einchipspeichersystem mit einem Dekoder für Pulswortleitungsverfahren

Info

Publication number
DE69721361D1
DE69721361D1 DE69721361T DE69721361T DE69721361D1 DE 69721361 D1 DE69721361 D1 DE 69721361D1 DE 69721361 T DE69721361 T DE 69721361T DE 69721361 T DE69721361 T DE 69721361T DE 69721361 D1 DE69721361 D1 DE 69721361D1
Authority
DE
Germany
Prior art keywords
decoder
word line
memory system
chip memory
line processes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69721361T
Other languages
English (en)
Other versions
DE69721361T2 (de
Inventor
Yoshiyuki Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Application granted granted Critical
Publication of DE69721361D1 publication Critical patent/DE69721361D1/de
Publication of DE69721361T2 publication Critical patent/DE69721361T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
DE69721361T 1996-02-28 1997-02-25 Einchipspeichersystem mit einem Dekoder für Pulswortleitungsverfahren Expired - Fee Related DE69721361T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8041392A JP2848314B2 (ja) 1996-02-28 1996-02-28 半導体記憶装置
JP4139296 1996-02-28

Publications (2)

Publication Number Publication Date
DE69721361D1 true DE69721361D1 (de) 2003-06-05
DE69721361T2 DE69721361T2 (de) 2004-03-18

Family

ID=12607112

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69721361T Expired - Fee Related DE69721361T2 (de) 1996-02-28 1997-02-25 Einchipspeichersystem mit einem Dekoder für Pulswortleitungsverfahren

Country Status (6)

Country Link
US (1) US5978308A (de)
EP (1) EP0793235B1 (de)
JP (1) JP2848314B2 (de)
KR (1) KR100263828B1 (de)
DE (1) DE69721361T2 (de)
TW (1) TW315466B (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0169267B1 (ko) * 1993-09-21 1999-02-01 사토 후미오 불휘발성 반도체 기억장치
JP2000285672A (ja) * 1999-03-26 2000-10-13 Fujitsu Ltd メモリデバイス
KR101499494B1 (ko) 2009-10-30 2015-03-06 가부시키가이샤 한도오따이 에네루기 켄큐쇼 논리 회로 및 반도체 장치
US8441885B2 (en) * 2011-03-18 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for memory word line driver
US8743651B2 (en) * 2012-06-08 2014-06-03 Freescale Semiconductor, Inc. Clocked memory with word line activation during a first portion of the clock cycle
US8861301B2 (en) * 2012-06-08 2014-10-14 Freescale Semiconductor, Inc. Clocked memory with latching predecoder circuitry

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0574167A (ja) * 1991-09-17 1993-03-26 Nec Corp 半導体記憶装置
EP0601715A1 (de) * 1992-12-11 1994-06-15 National Semiconductor Corporation Für den On-Chip-Speicherzugriff optimierter CPV-Kernbus
JPH07111084A (ja) * 1993-10-13 1995-04-25 Oki Micro Design Miyazaki:Kk 半導体集積回路装置
JP3080829B2 (ja) * 1994-02-17 2000-08-28 株式会社東芝 カスケード型メモリセル構造を有した多バンクシンクロナスメモリシステム
JPH07282597A (ja) * 1994-04-12 1995-10-27 Mitsubishi Electric Corp 半導体記憶装置
US5507024A (en) * 1994-05-16 1996-04-09 Allegro Microsystems, Inc. FM data-system radio receiver
JP2591907B2 (ja) * 1994-05-24 1997-03-19 日本電気アイシーマイコンシステム株式会社 読み出し専用半導体記憶装置のデコード回路
KR0158485B1 (ko) * 1995-03-31 1999-02-01 김광호 본딩옵션용 워드라인전압 승압회로
US5666324A (en) * 1996-03-15 1997-09-09 Mitsubishi Denki Kabushiki Kaisha Clock synchronous semiconductor memory device having current consumption reduced
JP3093632B2 (ja) * 1996-04-25 2000-10-03 日本電気アイシーマイコンシステム株式会社 半導体記憶装置

Also Published As

Publication number Publication date
TW315466B (de) 1997-09-11
EP0793235A2 (de) 1997-09-03
EP0793235B1 (de) 2003-05-02
US5978308A (en) 1999-11-02
DE69721361T2 (de) 2004-03-18
JPH09231753A (ja) 1997-09-05
KR970063262A (ko) 1997-09-12
JP2848314B2 (ja) 1999-01-20
EP0793235A3 (de) 2000-03-15
KR100263828B1 (ko) 2000-09-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee