DE69713084D1 - Verfahren und vorrichtung zur erzeugung einer programmierbaren verzögerung - Google Patents

Verfahren und vorrichtung zur erzeugung einer programmierbaren verzögerung

Info

Publication number
DE69713084D1
DE69713084D1 DE69713084T DE69713084T DE69713084D1 DE 69713084 D1 DE69713084 D1 DE 69713084D1 DE 69713084 T DE69713084 T DE 69713084T DE 69713084 T DE69713084 T DE 69713084T DE 69713084 D1 DE69713084 D1 DE 69713084D1
Authority
DE
Germany
Prior art keywords
delay cell
input delay
input
multiplexor
timing signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69713084T
Other languages
English (en)
Other versions
DE69713084T2 (de
Inventor
L Truebenbach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teradyne Inc
Original Assignee
Teradyne Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teradyne Inc filed Critical Teradyne Inc
Application granted granted Critical
Publication of DE69713084D1 publication Critical patent/DE69713084D1/de
Publication of DE69713084T2 publication Critical patent/DE69713084T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)
DE69713084T 1996-04-03 1997-03-28 Verfahren und vorrichtung zur erzeugung einer programmierbaren verzögerung Expired - Lifetime DE69713084T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/627,858 US5727021A (en) 1996-04-03 1996-04-03 Apparatus and method for providing a programmable delay with low fixed delay
PCT/US1997/005202 WO1997037235A1 (en) 1996-04-03 1997-03-28 Apparatus and method for providing a programmable delay

Publications (2)

Publication Number Publication Date
DE69713084D1 true DE69713084D1 (de) 2002-07-11
DE69713084T2 DE69713084T2 (de) 2003-03-13

Family

ID=24516444

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69713084T Expired - Lifetime DE69713084T2 (de) 1996-04-03 1997-03-28 Verfahren und vorrichtung zur erzeugung einer programmierbaren verzögerung

Country Status (9)

Country Link
US (1) US5727021A (de)
EP (1) EP0891559B1 (de)
JP (1) JP3836884B2 (de)
KR (1) KR100319194B1 (de)
AT (1) ATE218712T1 (de)
DE (1) DE69713084T2 (de)
ES (1) ES2176728T3 (de)
IL (1) IL126204A (de)
WO (1) WO1997037235A1 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5744995A (en) * 1996-04-17 1998-04-28 Xilinx, Inc. Six-input multiplexer wtih two gate levels and three memory cells
US6122719A (en) * 1997-10-31 2000-09-19 Silicon Spice Method and apparatus for retiming in a network of multiple context processing elements
US6150863A (en) * 1998-04-01 2000-11-21 Xilinx, Inc. User-controlled delay circuit for a programmable logic device
JP3616247B2 (ja) * 1998-04-03 2005-02-02 株式会社アドバンテスト Ｉｃ試験装置におけるスキュー調整方法及びこれに用いる疑似デバイス
US6107818A (en) * 1998-04-15 2000-08-22 Teradyne, Inc. High speed, real-time, state interconnect for automatic test equipment
US6636993B1 (en) * 1999-02-12 2003-10-21 Fujitsu Limited System and method for automatic deskew across a high speed, parallel interconnection
US6466626B1 (en) 1999-02-23 2002-10-15 International Business Machines Corporation Driver with in-situ variable compensation for cable attenuation
KR100301060B1 (ko) * 1999-07-22 2001-11-01 윤종용 웨이퍼 프로빙 장비 및 이를 이용한 웨이퍼 검사용 니들 교정방법
US6795931B1 (en) * 1999-09-30 2004-09-21 Micron Technology, Inc. Method and apparatus for an adjustable delay circuit having arranged serially coarse stages received by a fine delay stage
JP3984412B2 (ja) * 2000-05-26 2007-10-03 富士通株式会社 可変遅延回路および可変遅延回路を有する半導体集積回路
US6518812B1 (en) * 2000-07-20 2003-02-11 Silicon Graphics, Inc. Discrete delay line system and method
US20030048122A1 (en) * 2001-09-10 2003-03-13 Tauseef Kazi Universal programmable delay cell
US7036037B1 (en) * 2002-08-13 2006-04-25 Cypress Semiconductor Corp. Multi-bit deskewing of bus signals using a training pattern
EP1492290A3 (de) * 2003-06-26 2005-02-09 International Business Machines Corporation Bitausrichtung bei Mehrkanaldatenübertragung
US7606341B2 (en) * 2003-06-26 2009-10-20 International Business Machines Corporation Circuit for bit alignment in high speed multichannel data transmission
US20050046458A1 (en) * 2003-08-28 2005-03-03 Schroeder Charles G. Digital delay elements constructed in a programmable logic device
US7453302B2 (en) * 2003-12-23 2008-11-18 Infineon Technologies Ag Temperature compensated delay signals
DE102005020903B3 (de) * 2005-05-07 2006-11-09 Infineon Technologies Ag Steuerbare Verzögerungseinrichtung
US7457978B2 (en) * 2005-05-09 2008-11-25 Micron Technology, Inc. Adjustable byte lane offset for memory module to reduce skew
US20070096787A1 (en) * 2005-11-03 2007-05-03 United Memories, Inc. Method for improving the timing resolution of DLL controlled delay lines
US20080157385A1 (en) * 2006-12-29 2008-07-03 Heping Yue IC package with integral vertical passive delay cells
KR100889816B1 (ko) * 2007-03-27 2009-03-20 삼성전자주식회사 위상 정렬 장치 및 방법
US7685486B1 (en) * 2007-07-19 2010-03-23 Xilinx, Inc. Testing of an embedded multiplexer having a plurality of inputs
ATE505734T1 (de) 2007-08-22 2011-04-15 Verigy Pte Ltd Singapore Chipprüfvorrichtung und verfahren zum bereitstellen von timinginformationen
US8201011B1 (en) * 2007-09-26 2012-06-12 Oracle America, Inc. Timing optimization for paths in a processor
JP5298527B2 (ja) * 2007-12-24 2013-09-25 富士通セミコンダクター株式会社 可変遅延回路及びその制御方法
US8745337B2 (en) * 2007-12-31 2014-06-03 Teradyne, Inc. Apparatus and method for controlling memory overrun
US8008961B2 (en) * 2009-12-14 2011-08-30 Qualcomm Incorporated Adaptive clock generators, systems, and methods
US9000807B2 (en) * 2012-07-02 2015-04-07 Microsemi SoC Corporation On-chip probe circuit for detecting faults in an FPGA
CN103777528B (zh) * 2012-10-22 2016-08-24 英业达科技有限公司 印刷电路板与其信号时序控制方法
CN103777677B (zh) * 2012-10-22 2017-02-08 英业达科技有限公司 印刷电路板与其信号时序控制方法
US11183995B1 (en) * 2017-06-16 2021-11-23 Rambus Inc. High-resolution digitally controlled delay line

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4231104A (en) * 1978-04-26 1980-10-28 Teradyne, Inc. Generating timing signals
US4637018A (en) * 1984-08-29 1987-01-13 Burroughs Corporation Automatic signal delay adjustment method
US4700347A (en) * 1985-02-13 1987-10-13 Bolt Beranek And Newman Inc. Digital phase adjustment
FR2589651A1 (fr) * 1985-11-05 1987-05-07 Inf Milit Spatiale Aeronaut Ligne a retard a semi-conducteur pour circuit logique
US5274796A (en) * 1987-02-09 1993-12-28 Teradyne, Inc. Timing generator with edge generators, utilizing programmable delays, providing synchronized timing signals at non-integer multiples of a clock signal
JP2731875B2 (ja) * 1991-07-31 1998-03-25 株式会社アドバンテスト 可変遅延回路
US5313501A (en) * 1992-06-15 1994-05-17 Digital Equipment Corporation Method and apparatus for deskewing digital data
JP3550404B2 (ja) * 1992-09-10 2004-08-04 株式会社日立製作所 可変遅延回路及び可変遅延回路を用いたクロック信号供給装置
SE9203882L (sv) * 1992-12-22 1994-06-23 Ellemtel Utvecklings Ab Sätt och anordning för minimering av scew

Also Published As

Publication number Publication date
IL126204A0 (en) 1999-05-09
DE69713084T2 (de) 2003-03-13
ATE218712T1 (de) 2002-06-15
ES2176728T3 (es) 2002-12-01
EP0891559B1 (de) 2002-06-05
KR100319194B1 (ko) 2002-02-19
WO1997037235A1 (en) 1997-10-09
KR20000005251A (ko) 2000-01-25
EP0891559A1 (de) 1999-01-20
JP2000507702A (ja) 2000-06-20
IL126204A (en) 2001-08-08
US5727021A (en) 1998-03-10
JP3836884B2 (ja) 2006-10-25

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