DE69414744D1 - Verfahren und Schaltung zum Konfigurieren von Eingang/Ausgangsanordnungen - Google Patents

Verfahren und Schaltung zum Konfigurieren von Eingang/Ausgangsanordnungen

Info

Publication number
DE69414744D1
DE69414744D1 DE69414744T DE69414744T DE69414744D1 DE 69414744 D1 DE69414744 D1 DE 69414744D1 DE 69414744 T DE69414744 T DE 69414744T DE 69414744 T DE69414744 T DE 69414744T DE 69414744 D1 DE69414744 D1 DE 69414744D1
Authority
DE
Germany
Prior art keywords
circuit
output arrangements
configuring input
configuring
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69414744T
Other languages
English (en)
Other versions
DE69414744T2 (de
Inventor
Oscar Frederick Jones
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Promos Technologies Inc
Original Assignee
Nippon Steel Semiconductor Corp
United Memories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Semiconductor Corp, United Memories Inc filed Critical Nippon Steel Semiconductor Corp
Application granted granted Critical
Publication of DE69414744D1 publication Critical patent/DE69414744D1/de
Publication of DE69414744T2 publication Critical patent/DE69414744T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
DE69414744T 1993-03-26 1994-02-23 Verfahren und Schaltung zum Konfigurieren von Eingang/Ausgangsanordnungen Expired - Fee Related DE69414744T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/037,818 US5373470A (en) 1993-03-26 1993-03-26 Method and circuit for configuring I/O devices

Publications (2)

Publication Number Publication Date
DE69414744D1 true DE69414744D1 (de) 1999-01-07
DE69414744T2 DE69414744T2 (de) 1999-07-22

Family

ID=21896522

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69414744T Expired - Fee Related DE69414744T2 (de) 1993-03-26 1994-02-23 Verfahren und Schaltung zum Konfigurieren von Eingang/Ausgangsanordnungen

Country Status (5)

Country Link
US (1) US5373470A (de)
EP (1) EP0618584B1 (de)
JP (1) JP3089247B2 (de)
KR (1) KR100294965B1 (de)
DE (1) DE69414744T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6388314B1 (en) 1995-08-17 2002-05-14 Micron Technology, Inc. Single deposition layer metal dynamic random access memory
US5744870A (en) * 1996-06-07 1998-04-28 Micron Technology, Inc. Memory device with multiple input/output connections
KR100499844B1 (ko) * 1996-07-11 2006-04-21 텍사스 인스트루먼츠 인코포레이티드 정렬데이타저장장치및본딩패드를구비한ｄｒａｍ구조
US5900021A (en) * 1997-04-04 1999-05-04 United Memories, Inc. Pad input select circuit for use with bond options
US5903491A (en) 1997-06-09 1999-05-11 Micron Technology, Inc. Single deposition layer metal dynamic random access memory
US6295231B1 (en) 1998-07-17 2001-09-25 Kabushiki Kaisha Toshiba High-speed cycle clock-synchronous memory device
US7131033B1 (en) 2002-06-21 2006-10-31 Cypress Semiconductor Corp. Substrate configurable JTAG ID scheme
US7818640B1 (en) 2004-10-22 2010-10-19 Cypress Semiconductor Corporation Test system having a master/slave JTAG controller
US7908412B2 (en) * 2006-05-10 2011-03-15 Microsoft Corporation Buffer passing mechanisms
US7844764B2 (en) * 2007-10-01 2010-11-30 Honeywell International Inc. Unitary control module with adjustable input/output mapping
US8621377B2 (en) 2011-03-24 2013-12-31 Honeywell International Inc. Configurable HVAC controller terminal labeling
US20210098057A1 (en) * 2019-09-26 2021-04-01 Qualcomm Incorporated Sram low-power write driver

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60252979A (ja) * 1984-05-30 1985-12-13 Oki Electric Ind Co Ltd Ｃｍｏｓ入出力回路
US4649516A (en) * 1984-06-01 1987-03-10 International Business Machines Corp. Dynamic row buffer circuit for DRAM
US4577293A (en) * 1984-06-01 1986-03-18 International Business Machines Corporation Distributed, on-chip cache
JP2501344B2 (ja) * 1987-12-26 1996-05-29 株式会社東芝 デ―タ転送回路
US5146427A (en) * 1989-08-30 1992-09-08 Hitachi Ltd. High speed semiconductor memory having a direct-bypass signal path
US5068881A (en) * 1990-08-10 1991-11-26 Hewlett-Packard Company Scannable register with delay test capability
JP2530055B2 (ja) * 1990-08-30 1996-09-04 株式会社東芝 半導体集積回路

Also Published As

Publication number Publication date
KR100294965B1 (ko) 2001-09-17
JP3089247B2 (ja) 2000-09-18
DE69414744T2 (de) 1999-07-22
US5373470A (en) 1994-12-13
JPH06302697A (ja) 1994-10-28
EP0618584A1 (de) 1994-10-05
KR940020994A (ko) 1994-10-17
EP0618584B1 (de) 1998-11-25

Similar Documents

Publication Publication Date Title
DE69329502D1 (de) Verfahren zum Montieren von Chip-Bauteilen und Gerät dafür
DE69621517D1 (de) Integrierte monolithische Mikrowellenschaltung und Verfahren
DE69435286D1 (de) Verfahren und zusammensetzungen zum hervorrufen von schlaf
DE69416907D1 (de) Verfahren zum Verbinden von Elementen und Verbindungsanordnung
DE69300850T2 (de) Verfahren zum Montieren von Komponenten und Vorrichtung dafür.
DE69416011T2 (de) Wiederkonfigurierbare Rechnerschnittstelle und Verfahren
DE69430838D1 (de) Schaltung und Verfahren zur parallelen Verschiebung und Addition
DE69301225T2 (de) Verfahren und Schaltung zum Durchbrennen von Sicherung in einen integrierten Schaltkreis
DE69300853D1 (de) Verfahren zum Montieren von Bauteilen und Vorrichtung dafür.
DE69941143D1 (de) Verfahren zum Erzeugen von differentiellen drei Zuständen und differentieller Dreizustandsschaltung
DE69731700D1 (de) Arithmetischer Schaltkreis und arithmetisches Verfahren
DE69412624D1 (de) Verfahren und vorrichtungen zum verbinden von kabeln
DE69414744T2 (de) Verfahren und Schaltung zum Konfigurieren von Eingang/Ausgangsanordnungen
DE69205217D1 (de) Vorrichtung und Verfahren zum Zusammenbau von Schaltungsstrukturen.
DE69430035D1 (de) CMOS-Schaltung zum Ausführen von bollescher Funktionen
DE69717401T2 (de) Schaltung und Verfahren zum Erzeugen von Taktsignalen
DE69022224D1 (de) Eingabe-/abgabeanordnung und verfahren dazu.
DE69422078D1 (de) Schaltung und Verfahren zum Synchronisieren von Taktsignalen
DE69532061D1 (de) Verstärkerschaltung und Verfahren
DE69304493T2 (de) Verfahren und Gerät zum Montieren von Verbindern
DE69423170T2 (de) System und Verfahren zum Schaltungsentwurf
DE58905284D1 (de) Verfahren und schaltungsanordnung zum adressieren von prozessoreinheiten.
DE69501662T2 (de) Verfahren und Schaltung zum Testen von integriertem Speicher
DE59301408D1 (de) Verfahren und Schaltungsanordnung zum Dämpfen von mechanischen Schwingungen
DE59402504D1 (de) Verfahren und einrichtung zum automatisierten ausstoss von schnecken

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: MOSEL VITELIC INC., HSINCHU, TW

8328 Change in the person/name/address of the agent

Representative=s name: WEICKMANN & WEICKMANN, 81679 MUENCHEN

8327 Change in the person/name/address of the patent owner

Owner name: PROMOS TECHNOLOGIES, INC., HSINCHU, TW

8339 Ceased/non-payment of the annual fee