DE69700554D1 - Siliziumscheibe mit auf einer Oberfläche gestapelten polykristallinen Siliziumschichten,und ihr Herstellungsverfahren - Google Patents

Siliziumscheibe mit auf einer Oberfläche gestapelten polykristallinen Siliziumschichten,und ihr Herstellungsverfahren

Info

Publication number
DE69700554D1
DE69700554D1 DE69700554T DE69700554T DE69700554D1 DE 69700554 D1 DE69700554 D1 DE 69700554D1 DE 69700554 T DE69700554 T DE 69700554T DE 69700554 T DE69700554 T DE 69700554T DE 69700554 D1 DE69700554 D1 DE 69700554D1
Authority
DE
Germany
Prior art keywords
production process
layers stacked
silicon wafer
polycrystalline silicon
silicon layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69700554T
Other languages
English (en)
Other versions
DE69700554T2 (de
Inventor
Norihiro Kobayashi
Katsunori Koarai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of DE69700554D1 publication Critical patent/DE69700554D1/de
Application granted granted Critical
Publication of DE69700554T2 publication Critical patent/DE69700554T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12528—Semiconductor component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12674—Ge- or Si-base component

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Vapour Deposition (AREA)
  • Recrystallisation Techniques (AREA)
DE69700554T 1996-03-28 1997-03-26 Siliziumscheibe mit auf einer Oberfläche gestapelten polykristallinen Siliziumschichten,und ihr Herstellungsverfahren Expired - Fee Related DE69700554T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP09937196A JP3391184B2 (ja) 1996-03-28 1996-03-28 シリコンウエーハおよびその製造方法

Publications (2)

Publication Number Publication Date
DE69700554D1 true DE69700554D1 (de) 1999-11-04
DE69700554T2 DE69700554T2 (de) 2000-04-13

Family

ID=14245690

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69700554T Expired - Fee Related DE69700554T2 (de) 1996-03-28 1997-03-26 Siliziumscheibe mit auf einer Oberfläche gestapelten polykristallinen Siliziumschichten,und ihr Herstellungsverfahren

Country Status (6)

Country Link
US (1) US5863659A (de)
EP (1) EP0798770B1 (de)
JP (1) JP3391184B2 (de)
DE (1) DE69700554T2 (de)
MY (1) MY132487A (de)
TW (1) TW387115B (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3090201B2 (ja) * 1997-06-04 2000-09-18 日本電気株式会社 多結晶シリコン膜及び半導体装置
US6479166B1 (en) 1998-10-06 2002-11-12 Case Western Reserve University Large area polysilicon films with predetermined stress characteristics and method for producing same
US6268068B1 (en) * 1998-10-06 2001-07-31 Case Western Reserve University Low stress polysilicon film and method for producing same
JP2002231665A (ja) * 2001-02-06 2002-08-16 Sumitomo Metal Ind Ltd エピタキシャル膜付き半導体ウエーハの製造方法
US8846500B2 (en) 2010-12-13 2014-09-30 Semiconductor Components Industries, Llc Method of forming a gettering structure having reduced warpage and gettering a semiconductor wafer therewith
JP6100200B2 (ja) * 2014-04-24 2017-03-22 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP6118757B2 (ja) * 2014-04-24 2017-04-19 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP6353814B2 (ja) * 2015-06-09 2018-07-04 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
CN113035688B (zh) * 2019-12-09 2023-02-28 华润微电子（重庆）有限公司 一种半导体结构及其制作方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4053335A (en) * 1976-04-02 1977-10-11 International Business Machines Corporation Method of gettering using backside polycrystalline silicon
US4608096A (en) * 1983-04-04 1986-08-26 Monsanto Company Gettering
US5189508A (en) * 1988-03-30 1993-02-23 Nippon Steel Corporation Silicon wafer excelling in gettering ability and method for production thereof
JPH07120657B2 (ja) * 1988-04-05 1995-12-20 三菱電機株式会社 半導体基板
JP3063143B2 (ja) * 1990-10-29 2000-07-12 日本電気株式会社 Ｓｉ基板の製造方法
JP2649876B2 (ja) * 1991-05-08 1997-09-03 三菱電機株式会社 基 板
DE4304849C2 (de) * 1992-02-21 2000-01-27 Mitsubishi Electric Corp Halbleitervorrichtung und Verfahren zur Herstellung einer Halbleitervorrichtung
JPH0722428A (ja) * 1993-06-30 1995-01-24 Sony Corp シリコンウェハの製造方法及びシリコンウェハ
JP3232168B2 (ja) * 1993-07-02 2001-11-26 三菱電機株式会社 半導体基板およびその製造方法ならびにその半導体基板を用いた半導体装置

Also Published As

Publication number Publication date
JP3391184B2 (ja) 2003-03-31
TW387115B (en) 2000-04-11
MY132487A (en) 2007-10-31
DE69700554T2 (de) 2000-04-13
EP0798770A3 (de) 1998-02-25
EP0798770A2 (de) 1997-10-01
EP0798770B1 (de) 1999-09-29
JPH09266213A (ja) 1997-10-07
US5863659A (en) 1999-01-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee