DE69631946D1 - Herstellungsverfahren von Öffnungen in einer Passivierungsschicht einer Halbleiterschaltung - Google Patents
Herstellungsverfahren von Öffnungen in einer Passivierungsschicht einer HalbleiterschaltungInfo
- Publication number
- DE69631946D1 DE69631946D1 DE69631946T DE69631946T DE69631946D1 DE 69631946 D1 DE69631946 D1 DE 69631946D1 DE 69631946 T DE69631946 T DE 69631946T DE 69631946 T DE69631946 T DE 69631946T DE 69631946 D1 DE69631946 D1 DE 69631946D1
- Authority
- DE
- Germany
- Prior art keywords
- openings
- manufacturing
- passivation layer
- semiconductor circuit
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01007—Nitrogen [N]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01016—Sulfur [S]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01018—Argon [Ar]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0494—4th Group
- H01L2924/04941—TiN
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Wire Bonding (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US573171 | 1995-12-15 | ||
US08/573,171 US5960306A (en) | 1995-12-15 | 1995-12-15 | Process for forming a semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69631946D1 true DE69631946D1 (de) | 2004-04-29 |
DE69631946T2 DE69631946T2 (de) | 2005-01-20 |
Family
ID=24290930
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69631946T Expired - Lifetime DE69631946T2 (de) | 1995-12-15 | 1996-12-05 | Herstellungsverfahren von Öffnungen in einer Passivierungsschicht einer Halbleiterschaltung |
Country Status (7)
Country | Link |
---|---|
US (1) | US5960306A (de) |
EP (1) | EP0779654B1 (de) |
JP (1) | JP3954141B2 (de) |
KR (1) | KR100430696B1 (de) |
DE (1) | DE69631946T2 (de) |
SG (2) | SG86339A1 (de) |
TW (1) | TW325577B (de) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6965165B2 (en) | 1998-12-21 | 2005-11-15 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
US6255233B1 (en) | 1998-12-30 | 2001-07-03 | Intel Corporation | In-situ silicon nitride and silicon based oxide deposition with graded interface for damascene application |
US6261923B1 (en) * | 1999-01-04 | 2001-07-17 | Vanguard International Semiconductor Corporation | Method to solve the dishing issue in CMP planarization by using a nitride hard mask for local inverse etchback and CMP |
JP3387478B2 (ja) * | 1999-06-30 | 2003-03-17 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
US6383945B1 (en) * | 1999-10-29 | 2002-05-07 | Advanced Micro Devices, Inc. | High selectivity pad etch for thick topside stacks |
JP2001185845A (ja) * | 1999-12-15 | 2001-07-06 | Internatl Business Mach Corp <Ibm> | 電子部品の製造方法及び該電子部品 |
US6798073B2 (en) * | 2001-12-13 | 2004-09-28 | Megic Corporation | Chip structure and process for forming the same |
US6866943B2 (en) * | 2002-04-30 | 2005-03-15 | Infineon Technologies Ag | Bond pad structure comprising tungsten or tungsten compound layer on top of metallization level |
US7112288B2 (en) * | 2002-08-13 | 2006-09-26 | Texas Instruments Incorporated | Methods for inspection sample preparation |
US7030004B2 (en) * | 2003-11-10 | 2006-04-18 | 1St Silicon (Malaysia) Sdn Bhd | Method for forming bond pad openings |
CN102054685B (zh) * | 2009-10-29 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | 钝化层干法刻蚀方法 |
JP6099891B2 (ja) * | 2012-07-03 | 2017-03-22 | キヤノン株式会社 | ドライエッチング方法 |
MY181531A (en) * | 2013-01-18 | 2020-12-25 | Mimos Berhad | Method of fabricating a bond pad in a semiconductor device |
JP6111907B2 (ja) * | 2013-07-05 | 2017-04-12 | 三菱電機株式会社 | 半導体装置の製造方法 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4005455A (en) * | 1974-08-21 | 1977-01-25 | Intel Corporation | Corrosive resistant semiconductor interconnect pad |
JPS57113235A (en) * | 1980-12-29 | 1982-07-14 | Nec Corp | Semiconductor device |
US4446194A (en) * | 1982-06-21 | 1984-05-01 | Motorola, Inc. | Dual layer passivation |
US4426246A (en) * | 1982-07-26 | 1984-01-17 | Bell Telephone Laboratories, Incorporated | Plasma pretreatment with BCl3 to remove passivation formed by fluorine-etch |
US4620986A (en) * | 1984-11-09 | 1986-11-04 | Intel Corporation | MOS rear end processing |
US4988423A (en) * | 1987-06-19 | 1991-01-29 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating interconnection structure |
US4824803A (en) * | 1987-06-22 | 1989-04-25 | Standard Microsystems Corporation | Multilayer metallization method for integrated circuits |
US4911786A (en) * | 1989-04-26 | 1990-03-27 | International Business Machines Corporation | Method of etching polyimides and resulting passivation structure |
US5246782A (en) * | 1990-12-10 | 1993-09-21 | The Dow Chemical Company | Laminates of polymers having perfluorocyclobutane rings and polymers containing perfluorocyclobutane rings |
US5421891A (en) * | 1989-06-13 | 1995-06-06 | Plasma & Materials Technologies, Inc. | High density plasma deposition and etching apparatus |
US5443998A (en) * | 1989-08-01 | 1995-08-22 | Cypress Semiconductor Corp. | Method of forming a chlorinated silicon nitride barrier layer |
US5120671A (en) * | 1990-11-29 | 1992-06-09 | Intel Corporation | Process for self aligning a source region with a field oxide region and a polysilicon gate |
US5514616A (en) * | 1991-08-26 | 1996-05-07 | Lsi Logic Corporation | Depositing and densifying glass to planarize layers in semi-conductor devices based on CMOS structures |
US5470693A (en) * | 1992-02-18 | 1995-11-28 | International Business Machines Corporation | Method of forming patterned polyimide films |
US5244817A (en) * | 1992-08-03 | 1993-09-14 | Eastman Kodak Company | Method of making backside illuminated image sensors |
US5825078A (en) * | 1992-09-23 | 1998-10-20 | Dow Corning Corporation | Hermetic protection for integrated circuits |
US5380401A (en) * | 1993-01-14 | 1995-01-10 | Micron Technology, Inc. | Method to remove fluorine residues from bond pads |
JPH0758107A (ja) * | 1993-08-18 | 1995-03-03 | Toshiba Corp | 半導体装置の製造方法 |
US5433823A (en) * | 1993-09-30 | 1995-07-18 | Cain; John L. | Selective dry-etching of bi-layer passivation films |
US5512130A (en) * | 1994-03-09 | 1996-04-30 | Texas Instruments Incorporated | Method and apparatus of etching a clean trench in a semiconductor material |
-
1995
- 1995-12-15 US US08/573,171 patent/US5960306A/en not_active Expired - Lifetime
-
1996
- 1996-10-16 TW TW085112658A patent/TW325577B/zh not_active IP Right Cessation
- 1996-10-25 SG SG9804731A patent/SG86339A1/en unknown
- 1996-10-25 SG SG1996010930A patent/SG45511A1/en unknown
- 1996-12-05 EP EP96119527A patent/EP0779654B1/de not_active Expired - Lifetime
- 1996-12-05 DE DE69631946T patent/DE69631946T2/de not_active Expired - Lifetime
- 1996-12-09 JP JP34470096A patent/JP3954141B2/ja not_active Expired - Fee Related
- 1996-12-13 KR KR1019960064969A patent/KR100430696B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0779654A3 (de) | 1998-04-08 |
SG45511A1 (en) | 1998-01-16 |
TW325577B (en) | 1998-01-21 |
SG86339A1 (en) | 2002-02-19 |
US5960306A (en) | 1999-09-28 |
EP0779654B1 (de) | 2004-03-24 |
JP3954141B2 (ja) | 2007-08-08 |
KR100430696B1 (ko) | 2004-08-31 |
DE69631946T2 (de) | 2005-01-20 |
JPH09181115A (ja) | 1997-07-11 |
EP0779654A2 (de) | 1997-06-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: FREESCALE SEMICONDUCTOR, INC., AUSTIN, TEX., US |