DE69636808D1 - Herstellungsverfahren von Stützen in einer isolierenden Schicht auf einem Halbleiterwafer - Google Patents

Herstellungsverfahren von Stützen in einer isolierenden Schicht auf einem Halbleiterwafer

Info

Publication number
DE69636808D1
DE69636808D1 DE69636808T DE69636808T DE69636808D1 DE 69636808 D1 DE69636808 D1 DE 69636808D1 DE 69636808 T DE69636808 T DE 69636808T DE 69636808 T DE69636808 T DE 69636808T DE 69636808 D1 DE69636808 D1 DE 69636808D1
Authority
DE
Germany
Prior art keywords
supports
insulating layer
production method
semiconductor wafer
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69636808T
Other languages
English (en)
Other versions
DE69636808T2 (de
Inventor
Jeffrey Peter Gambino
Mark Anthony Jaso
Larry Alan Nesbit
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69636808D1 publication Critical patent/DE69636808D1/de
Publication of DE69636808T2 publication Critical patent/DE69636808T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69636808T 1995-11-14 1996-11-08 Herstellungsverfahren von Stützen in einer isolierenden Schicht auf einem Halbleiterwafer Expired - Lifetime DE69636808T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/557,225 US5573633A (en) 1995-11-14 1995-11-14 Method of chemically mechanically polishing an electronic component
US557225 1995-11-14

Publications (2)

Publication Number Publication Date
DE69636808D1 true DE69636808D1 (de) 2007-02-15
DE69636808T2 DE69636808T2 (de) 2007-11-08

Family

ID=24224534

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69636808T Expired - Lifetime DE69636808T2 (de) 1995-11-14 1996-11-08 Herstellungsverfahren von Stützen in einer isolierenden Schicht auf einem Halbleiterwafer

Country Status (4)

Country Link
US (2) US5573633A (de)
EP (1) EP0774781B1 (de)
JP (1) JP3251867B2 (de)
DE (1) DE69636808T2 (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
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JPH08203998A (ja) * 1995-01-20 1996-08-09 Sony Corp 多層配線の形成方法
US5824576A (en) * 1996-02-23 1998-10-20 Micron Technology, Inc. Method of forming complementary type conductive regions on a substrate
US6413870B1 (en) * 1996-09-30 2002-07-02 International Business Machines Corporation Process of removing CMP scratches by BPSG reflow and integrated circuit chip formed thereby
US5973385A (en) * 1996-10-24 1999-10-26 International Business Machines Corporation Method for suppressing pattern distortion associated with BPSG reflow and integrated circuit chip formed thereby
KR100266749B1 (ko) * 1997-06-11 2000-09-15 윤종용 반도체 장치의 콘택 플러그 형성 방법
JP3390329B2 (ja) * 1997-06-27 2003-03-24 日本電気株式会社 半導体装置およびその製造方法
US5915175A (en) * 1997-06-27 1999-06-22 Siemens Aktiengesellschaft Mitigation of CMP-induced BPSG surface damage by an integrated anneal and silicon dioxide deposition
US6362101B2 (en) * 1997-11-24 2002-03-26 United Microelectronics Corp. Chemical mechanical polishing methods using low pH slurry mixtures
US6960818B1 (en) * 1997-12-30 2005-11-01 Siemens Aktiengesellschaft Recessed shallow trench isolation structure nitride liner and method for making same
US6200896B1 (en) 1998-01-22 2001-03-13 Cypress Semiconductor Corporation Employing an acidic liquid and an abrasive surface to polish a semiconductor topography
US6143663A (en) * 1998-01-22 2000-11-07 Cypress Semiconductor Corporation Employing deionized water and an abrasive surface to polish a semiconductor topography
US6171180B1 (en) 1998-03-31 2001-01-09 Cypress Semiconductor Corporation Planarizing a trench dielectric having an upper surface within a trench spaced below an adjacent polish stop surface
US6200901B1 (en) 1998-06-10 2001-03-13 Micron Technology, Inc. Polishing polymer surfaces on non-porous CMP pads
US6265315B1 (en) * 1998-06-24 2001-07-24 Taiwan Semiconductor Manufacturing Company Method for improving chemical/mechanical polish uniformity over rough topography for semiconductor integrated circuits
JP2000040679A (ja) 1998-07-24 2000-02-08 Hitachi Ltd 半導体集積回路装置の製造方法
US5972124A (en) 1998-08-31 1999-10-26 Advanced Micro Devices, Inc. Method for cleaning a surface of a dielectric material
US6534378B1 (en) 1998-08-31 2003-03-18 Cypress Semiconductor Corp. Method for forming an integrated circuit device
US6232231B1 (en) 1998-08-31 2001-05-15 Cypress Semiconductor Corporation Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect
US6566249B1 (en) 1998-11-09 2003-05-20 Cypress Semiconductor Corp. Planarized semiconductor interconnect topography and method for polishing a metal layer to form wide interconnect structures
US6100168A (en) * 1998-11-16 2000-08-08 Industrial Technology Research Institute Location selective transmutation doping on silicon wafers using high energy deuterons
DE19910461A1 (de) 1999-03-10 2000-09-14 Starck H C Gmbh Co Kg Mit Kobalthydroxid beschichtetes Nickelhydroxid
US6555466B1 (en) 1999-03-29 2003-04-29 Speedfam Corporation Two-step chemical-mechanical planarization for damascene structures on semiconductor wafers
US6235633B1 (en) 1999-04-12 2001-05-22 Taiwan Semiconductor Manufacturing Company Method for making tungsten metal plugs in a polymer low-K intermetal dielectric layer using an improved two-step chemical/mechanical polishing process
US6211086B1 (en) * 1999-06-08 2001-04-03 United Microelectronics Corp. Method of avoiding CMP caused residue on wafer edge uncompleted field
US6291296B1 (en) * 1999-10-12 2001-09-18 Advanced Micro Devices, Inc. Method for removing anti-reflective coating layer using plasma etch process before contact CMP
US6136649A (en) * 1999-10-12 2000-10-24 Advanced Micro Devices, Inc. Method for removing anti-reflective coating layer using plasma etch process after contact CMP
JP2002093811A (ja) * 2000-09-11 2002-03-29 Sony Corp 電極および半導体装置の製造方法
US6413846B1 (en) * 2000-11-14 2002-07-02 Advanced Micro Devices, Inc. Contact each methodology and integration scheme
US6576507B1 (en) 2000-11-14 2003-06-10 International Business Machines Corporation Selectively removable filler layer for BiCMOS process
US6969684B1 (en) 2001-04-30 2005-11-29 Cypress Semiconductor Corp. Method of making a planarized semiconductor structure
US6699356B2 (en) 2001-08-17 2004-03-02 Applied Materials, Inc. Method and apparatus for chemical-mechanical jet etching of semiconductor structures
US6828678B1 (en) 2002-03-29 2004-12-07 Silicon Magnetic Systems Semiconductor topography with a fill material arranged within a plurality of valleys associated with the surface roughness of the metal layer
DE102004001853B3 (de) * 2004-01-13 2005-07-21 Infineon Technologies Ag Verfahren zum Herstellen von Kontaktierungsanschlüssen
KR20130090209A (ko) * 2012-02-03 2013-08-13 삼성전자주식회사 기판처리장치 및 기판처리방법
US9034752B2 (en) * 2013-01-03 2015-05-19 Micron Technology, Inc. Methods of exposing conductive vias of semiconductor devices and associated structures
US9633962B2 (en) 2013-10-08 2017-04-25 Globalfoundries Inc. Plug via formation with grid features in the passivation layer

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3740835A (en) * 1970-08-31 1973-06-26 Fairchild Camera Instr Co Method of forming semiconductor device contacts
US4589928A (en) * 1984-08-21 1986-05-20 At&T Bell Laboratories Method of making semiconductor integrated circuits having backside gettered with phosphorus
US5084413A (en) * 1986-04-15 1992-01-28 Matsushita Electric Industrial Co., Ltd. Method for filling contact hole
US5008730A (en) * 1988-10-03 1991-04-16 International Business Machines Corporation Contact stud structure for semiconductor devices
US5008216A (en) * 1988-10-03 1991-04-16 International Business Machines Corporation Process for improved contact stud structure for semiconductor devices
US5143820A (en) * 1989-10-31 1992-09-01 International Business Machines Corporation Method for fabricating high circuit density, self-aligned metal linens to contact windows
US5026666A (en) * 1989-12-28 1991-06-25 At&T Bell Laboratories Method of making integrated circuits having a planarized dielectric
US5244534A (en) * 1992-01-24 1993-09-14 Micron Technology, Inc. Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs
US5252516A (en) * 1992-02-20 1993-10-12 International Business Machines Corporation Method for producing interlevel stud vias
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5328553A (en) * 1993-02-02 1994-07-12 Motorola Inc. Method for fabricating a semiconductor device having a planar surface

Also Published As

Publication number Publication date
JPH09167798A (ja) 1997-06-24
US5573633A (en) 1996-11-12
US5795826A (en) 1998-08-18
EP0774781A2 (de) 1997-05-21
DE69636808T2 (de) 2007-11-08
JP3251867B2 (ja) 2002-01-28
EP0774781A3 (de) 1998-04-08
EP0774781B1 (de) 2007-01-03

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