DE69615776D1 - Herstellungsmethode einer durch eine anti-sicherung programmierbaren halbleiteranordnung - Google Patents

Herstellungsmethode einer durch eine anti-sicherung programmierbaren halbleiteranordnung

Info

Publication number
DE69615776D1
DE69615776D1 DE69615776T DE69615776T DE69615776D1 DE 69615776 D1 DE69615776 D1 DE 69615776D1 DE 69615776 T DE69615776 T DE 69615776T DE 69615776 T DE69615776 T DE 69615776T DE 69615776 D1 DE69615776 D1 DE 69615776D1
Authority
DE
Germany
Prior art keywords
fuse
production method
semiconductor arrangement
programmable
arrangement programmable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69615776T
Other languages
English (en)
Other versions
DE69615776T2 (de
Inventor
De Zaldivar Jose Solo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Application granted granted Critical
Publication of DE69615776D1 publication Critical patent/DE69615776D1/de
Publication of DE69615776T2 publication Critical patent/DE69615776T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885—Hot carrier injection from the channel
DE69615776T 1995-04-21 1996-03-18 Herstellungsmethode einer durch eine anti-sicherung programmierbaren halbleiteranordnung Expired - Fee Related DE69615776T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP95201019 1995-04-21
PCT/IB1996/000240 WO1996033511A2 (en) 1995-04-21 1996-03-18 Method of manufacturing a progammable semiconductor device in the form of an anti-fuse

Publications (2)

Publication Number Publication Date
DE69615776D1 true DE69615776D1 (de) 2001-11-15
DE69615776T2 DE69615776T2 (de) 2002-07-11

Family

ID=8220212

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69615776T Expired - Fee Related DE69615776T2 (de) 1995-04-21 1996-03-18 Herstellungsmethode einer durch eine anti-sicherung programmierbaren halbleiteranordnung

Country Status (7)

Country Link
US (1) US5610084A (de)
EP (1) EP0766870B1 (de)
JP (1) JPH10502219A (de)
KR (1) KR970704243A (de)
DE (1) DE69615776T2 (de)
TW (1) TW287301B (de)
WO (1) WO1996033511A2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5986322A (en) * 1995-06-06 1999-11-16 Mccollum; John L. Reduced leakage antifuse structure
US6103555A (en) * 1996-06-10 2000-08-15 Integrated Device Technology, Inc. Method of improving the reliability of low-voltage programmable antifuse
US5872049A (en) * 1996-06-19 1999-02-16 Advanced Micro Devices, Inc. Nitrogenated gate structure for improved transistor performance and method for making same
US5937303A (en) * 1997-10-29 1999-08-10 Advanced Micro Devices High dielectric constant gate dielectric integrated with nitrogenated gate electrode
US5858840A (en) 1997-12-22 1999-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming sharp beak of poly by nitrogen implant to improve erase speed for split-gate flash
US6188101B1 (en) * 1998-01-14 2001-02-13 Advanced Micro Devices, Inc. Flash EPROM cell with reduced short channel effect and method for providing same
US5972751A (en) * 1998-08-28 1999-10-26 Advanced Micro Devices, Inc. Methods and arrangements for introducing nitrogen into a tunnel oxide in a non-volatile semiconductor memory device
US6235590B1 (en) 1998-12-18 2001-05-22 Lsi Logic Corporation Fabrication of differential gate oxide thicknesses on a single integrated circuit chip
US6255169B1 (en) * 1999-02-22 2001-07-03 Advanced Micro Devices, Inc. Process for fabricating a high-endurance non-volatile memory device
US6096580A (en) * 1999-09-24 2000-08-01 International Business Machines Corporation Low programming voltage anti-fuse
US6753590B2 (en) * 2002-07-08 2004-06-22 International Business Machines Corporation High impedance antifuse
US20040051162A1 (en) * 2002-09-13 2004-03-18 International Business Machines Corporation Structure and method of providing reduced programming voltage antifuse
US7026217B1 (en) * 2003-10-29 2006-04-11 Lsi Logic Corporation Method of forming an antifuse on a semiconductor substrate using wet oxidation of a nitrided substrate
US7420242B2 (en) * 2005-08-31 2008-09-02 Macronix International Co., Ltd. Stacked bit line dual word line nonvolatile memory
US8049299B2 (en) * 2009-02-25 2011-11-01 Freescale Semiconductor, Inc. Antifuses with curved breakdown regions
EP3314647A4 (de) * 2015-06-25 2019-02-20 Intel Corporation Kontrollierte modifikation einer antifuse-programmierspannung

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5951127B2 (ja) * 1974-08-23 1984-12-12 株式会社日立製作所 半導体装置の製造方法
JPS52139371A (en) * 1976-05-17 1977-11-21 Nec Corp Production of semiconductor integrated circuit device
JPS5854638A (ja) * 1981-09-28 1983-03-31 Mitsubishi Electric Corp 半導体装置の製造方法
JPS6258673A (ja) * 1985-09-09 1987-03-14 Fujitsu Ltd 半導体記憶装置
US4757359A (en) * 1986-04-07 1988-07-12 American Microsystems, Inc. Thin oxide fuse
US4774197A (en) * 1986-06-17 1988-09-27 Advanced Micro Devices, Inc. Method of improving silicon dioxide
JPS63205944A (ja) * 1987-02-23 1988-08-25 Matsushita Electronics Corp Ｍｏｓ集積回路の製造方法
JPS63215061A (ja) * 1987-03-04 1988-09-07 Matsushita Electronics Corp 半導体集積回路の製造方法
EP0509631A1 (de) * 1991-04-18 1992-10-21 Actel Corporation Antischmelzsicherungen mit minimalischen Oberflächen
JP2905032B2 (ja) * 1992-05-12 1999-06-14 シャープ株式会社 金属配線の製造方法
JPH08502857A (ja) * 1992-08-21 1996-03-26 ジリンクス，インコーポレーテッド アンチヒューズ構造およびその形成方法
JP3102223B2 (ja) * 1993-09-24 2000-10-23 住友金属工業株式会社 シリコン基板の酸化方法

Also Published As

Publication number Publication date
KR970704243A (ko) 1997-08-09
WO1996033511A3 (en) 1996-12-19
WO1996033511A2 (en) 1996-10-24
DE69615776T2 (de) 2002-07-11
US5610084A (en) 1997-03-11
EP0766870B1 (de) 2001-10-10
JPH10502219A (ja) 1998-02-24
TW287301B (de) 1996-10-01
EP0766870A2 (de) 1997-04-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee