DE69631112T2 - Testverfahren für eine elektronische schaltung durch logisches verbinden von taktsignalen und elektronische schaltung mit vorrichtung für ein solches testverfahren - Google Patents

Testverfahren für eine elektronische schaltung durch logisches verbinden von taktsignalen und elektronische schaltung mit vorrichtung für ein solches testverfahren Download PDF

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Publication number
DE69631112T2
DE69631112T2 DE69631112T DE69631112T DE69631112T2 DE 69631112 T2 DE69631112 T2 DE 69631112T2 DE 69631112 T DE69631112 T DE 69631112T DE 69631112 T DE69631112 T DE 69631112T DE 69631112 T2 DE69631112 T2 DE 69631112T2
Authority
DE
Germany
Prior art keywords
electronic circuit
test method
clock signals
logically connecting
connecting clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69631112T
Other languages
English (en)
Other versions
DE69631112D1 (de
Inventor
Manoj Sachdev
Botjo Atzema
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Application granted granted Critical
Publication of DE69631112D1 publication Critical patent/DE69631112D1/de
Publication of DE69631112T2 publication Critical patent/DE69631112T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69631112T 1995-07-06 1996-07-01 Testverfahren für eine elektronische schaltung durch logisches verbinden von taktsignalen und elektronische schaltung mit vorrichtung für ein solches testverfahren Expired - Fee Related DE69631112T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP95201853 1995-07-06
PCT/IB1996/000626 WO1997002493A2 (en) 1995-07-06 1996-07-01 A method for testing an electronic circuit by logically combining clock signals, and an electronic circuit provided with facilities for such testing

Publications (2)

Publication Number Publication Date
DE69631112D1 DE69631112D1 (de) 2004-01-29
DE69631112T2 true DE69631112T2 (de) 2004-10-21

Family

ID=8220460

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69631112T Expired - Fee Related DE69631112T2 (de) 1995-07-06 1996-07-01 Testverfahren für eine elektronische schaltung durch logisches verbinden von taktsignalen und elektronische schaltung mit vorrichtung für ein solches testverfahren

Country Status (6)

Country Link
US (1) US5781025A (de)
EP (1) EP0780037B1 (de)
JP (1) JPH10505683A (de)
KR (1) KR970705760A (de)
DE (1) DE69631112T2 (de)
WO (1) WO1997002493A2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2775526B1 (fr) 1998-02-27 2000-04-21 Sgs Thomson Microelectronics Dispositif de test en production des caracteristiques dynamiques de composants utilisant des transmissions serie
US6955831B2 (en) 2000-05-09 2005-10-18 Her Majesty The Queen In Right Of Canada As Represented By The Minister Of Fisheries And Oceans Protein and lipid sources for use in aquafeeds and animal feeds and a process for their preparation
DE102004034606B4 (de) * 2004-07-16 2012-03-29 Infineon Technologies Ag Schaltungsanordnung aus einer elektronischen Testschaltung für einen zu testenden Transceiver und aus dem zu testenden Transceiver sowie Verfahren zum Prüfen eines Transceivers
KR101446559B1 (ko) * 2008-03-24 2014-10-06 삼성전자주식회사 3차원 영상 시청을 위한 신호생성방법 및 이를 적용한영상시청장치
US10248520B2 (en) * 2015-09-25 2019-04-02 Oracle International Corporation High speed functional test vectors in low power test conditions of a digital integrated circuit
US10567214B2 (en) * 2018-04-30 2020-02-18 Cirrus Logic, Inc. Communication circuitry and control circuitry thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4542509A (en) * 1983-10-31 1985-09-17 International Business Machines Corporation Fault testing a clock distribution network
JPS62220879A (ja) * 1986-03-22 1987-09-29 Hitachi Ltd 半導体装置
US5206861A (en) * 1990-08-28 1993-04-27 International Business Machines Corporation System timing analysis by self-timing logic and clock paths
US5406132A (en) * 1992-01-21 1995-04-11 Advantest Corporation Waveform shaper for semiconductor testing devices
JP2522140B2 (ja) * 1992-11-18 1996-08-07 日本電気株式会社 論理回路
FR2711286B1 (fr) * 1993-10-11 1996-01-05 Sgs Thomson Microelectronics Dispositif de surveillance du déphasage entre deux signaux d'horloge.
US5428626A (en) * 1993-10-18 1995-06-27 Tektronix, Inc. Timing analyzer for embedded testing
US5606564A (en) * 1995-05-19 1997-02-25 Cirrus Logic Inc. Test logic circuit and method for verifying internal logic of an integrated circuit

Also Published As

Publication number Publication date
EP0780037A2 (de) 1997-06-25
JPH10505683A (ja) 1998-06-02
WO1997002493A2 (en) 1997-01-23
KR970705760A (ko) 1997-10-09
WO1997002493A3 (en) 1997-03-06
US5781025A (en) 1998-07-14
EP0780037B1 (de) 2003-12-17
DE69631112D1 (de) 2004-01-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN

8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL

8339 Ceased/non-payment of the annual fee