DE69622126D1 - Speichervorrichtung mit verringerter Anzahl von Sicherungen - Google Patents

Speichervorrichtung mit verringerter Anzahl von Sicherungen

Info

Publication number
DE69622126D1
DE69622126D1 DE69622126T DE69622126T DE69622126D1 DE 69622126 D1 DE69622126 D1 DE 69622126D1 DE 69622126 T DE69622126 T DE 69622126T DE 69622126 T DE69622126 T DE 69622126T DE 69622126 D1 DE69622126 D1 DE 69622126D1
Authority
DE
Germany
Prior art keywords
address
redundant
received
backups
storage device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69622126T
Other languages
English (en)
Other versions
DE69622126T2 (de
Inventor
Ray Pinkham
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix America Inc
Original Assignee
Hyundai Electronics America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics America Inc filed Critical Hyundai Electronics America Inc
Publication of DE69622126D1 publication Critical patent/DE69622126D1/de
Application granted granted Critical
Publication of DE69622126T2 publication Critical patent/DE69622126T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/812—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a reduced amount of fuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
    • G11C29/818—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for dual-port memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/86—Masking faults in memories by using spares or by reconfiguring in serial access memories, e.g. shift registers, CCDs, bubble memories

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Static Random-Access Memory (AREA)
DE69622126T 1995-10-31 1996-10-30 Speichervorrichtung mit verringerter Anzahl von Sicherungen Expired - Lifetime DE69622126T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/550,587 US5646896A (en) 1995-10-31 1995-10-31 Memory device with reduced number of fuses

Publications (2)

Publication Number Publication Date
DE69622126D1 true DE69622126D1 (de) 2002-08-08
DE69622126T2 DE69622126T2 (de) 2003-01-30

Family

ID=24197790

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69622126T Expired - Lifetime DE69622126T2 (de) 1995-10-31 1996-10-30 Speichervorrichtung mit verringerter Anzahl von Sicherungen

Country Status (7)

Country Link
US (1) US5646896A (de)
EP (1) EP0772202B1 (de)
JP (1) JP3190580B2 (de)
KR (1) KR100278086B1 (de)
CN (1) CN1114927C (de)
DE (1) DE69622126T2 (de)
TW (1) TW326530B (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2850953B2 (ja) * 1996-07-30 1999-01-27 日本電気株式会社 半導体装置
US5953745A (en) * 1996-11-27 1999-09-14 International Business Machines Corporation Redundant memory array
CA2202692C (en) * 1997-04-14 2006-06-13 Mosaid Technologies Incorporated Column redundancy in semiconductor memories
DE69826075D1 (de) * 1997-06-30 2004-10-14 Siemens Ag Technik zur Reduzierung der Anzahl der Schmelzsicherungen bei einer DRAM mit Redundanz
US6055611A (en) * 1997-07-09 2000-04-25 Micron Technology, Inc. Method and apparatus for enabling redundant memory
KR100480567B1 (ko) * 1997-10-27 2005-09-30 삼성전자주식회사 반도체메모리장치
KR100486216B1 (ko) * 1997-11-06 2005-08-01 삼성전자주식회사 반도체메모리장치의리던던시메모리셀제어회로
US6005813A (en) * 1997-11-12 1999-12-21 Micron Technology, Inc. Device and method for repairing a semiconductor memory
CA2223222C (en) * 1997-11-28 2006-05-02 Mosaid Technologies Incorporated Data-bit redundancy for semiconductor memories
US6144591A (en) * 1997-12-30 2000-11-07 Mosaid Technologies Incorporated Redundancy selection circuit for semiconductor memories
US6137735A (en) * 1998-10-30 2000-10-24 Mosaid Technologies Incorporated Column redundancy circuit with reduced signal path delay
JP2001167595A (ja) * 1999-12-08 2001-06-22 Mitsubishi Electric Corp 半導体記憶装置
KR100364817B1 (ko) * 2001-02-02 2002-12-16 주식회사 하이닉스반도체 로우 리던던시 회로
JP3863410B2 (ja) * 2001-11-12 2006-12-27 富士通株式会社 半導体メモリ
US7111193B1 (en) 2002-07-30 2006-09-19 Taiwan Semiconductor Manufacturing Co. Ltd. Semiconductor memory having re-configurable fuse set for redundancy repair
JP2004102508A (ja) * 2002-09-06 2004-04-02 Renesas Technology Corp 半導体記憶装置
TW574703B (en) * 2002-09-09 2004-02-01 High Bandwidth Access Taiwan I A memory structure with redundant memory for accessing data sequentially
US20040123181A1 (en) * 2002-12-20 2004-06-24 Moon Nathan I. Self-repair of memory arrays using preallocated redundancy (PAR) architecture
KR100784087B1 (ko) 2006-05-04 2007-12-10 주식회사 하이닉스반도체 반도체 메모리 장치의 리페어 회로
JP2008084453A (ja) * 2006-09-28 2008-04-10 Sanyo Electric Co Ltd ヒューズ読み出し回路
KR100902122B1 (ko) * 2007-04-17 2009-06-09 주식회사 하이닉스반도체 반도체 메모리장치
CN101640074B (zh) * 2008-07-29 2013-01-23 旭曜科技股份有限公司 存储器修补电路及使用其的仿双端口静态随机存取存储器
KR20180068095A (ko) * 2016-12-13 2018-06-21 에스케이하이닉스 주식회사 반도체 장치 및 이를 포함하는 반도체 시스템
CN117079695B (zh) * 2023-10-11 2024-01-23 浙江力积存储科技有限公司 用在存储阵列中的熔断器单元及其处理方法、存储阵列

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4747081A (en) 1983-12-30 1988-05-24 Texas Instruments Incorporated Video display system using memory with parallel and serial access employing serial shift registers selected by column address
US4667313A (en) * 1985-01-22 1987-05-19 Texas Instruments Incorporated Serially accessed semiconductor memory with tapped shift register
US4648077A (en) 1985-01-22 1987-03-03 Texas Instruments Incorporated Video serial accessed memory with midline load
US4636986B1 (en) 1985-01-22 1999-12-07 Texas Instruments Inc Separately addressable memory arrays in a multiple array semiconductor chip
US4719601A (en) * 1986-05-02 1988-01-12 International Business Machine Corporation Column redundancy for two port random access memory
US4817058A (en) * 1987-05-21 1989-03-28 Texas Instruments Incorporated Multiple input/output read/write memory having a multiple-cycle write mask
JPH02246087A (ja) * 1989-03-20 1990-10-01 Hitachi Ltd 半導体記憶装置ならびにその冗長方式及びレイアウト方式
FR2666917B1 (fr) * 1990-09-14 1994-02-18 Samsung Electronics Co Ltd Dispositif de memorisation a double acces.
KR960016807B1 (ko) * 1994-06-30 1996-12-21 삼성전자 주식회사 반도체 메모리 장치의 리던던시 회로

Also Published As

Publication number Publication date
EP0772202B1 (de) 2002-07-03
CN1155150A (zh) 1997-07-23
EP0772202A3 (de) 1999-07-07
JP3190580B2 (ja) 2001-07-23
US5646896A (en) 1997-07-08
EP0772202A2 (de) 1997-05-07
JPH09185896A (ja) 1997-07-15
KR100278086B1 (ko) 2001-01-15
DE69622126T2 (de) 2003-01-30
TW326530B (en) 1998-02-11
CN1114927C (zh) 2003-07-16

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Legal Events

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8364 No opposition during term of opposition