DE69602946D1 - Pipelineadressiertes speichersystem und verfahren zu dessen betrieb - Google Patents
Pipelineadressiertes speichersystem und verfahren zu dessen betriebInfo
- Publication number
- DE69602946D1 DE69602946D1 DE69602946T DE69602946T DE69602946D1 DE 69602946 D1 DE69602946 D1 DE 69602946D1 DE 69602946 T DE69602946 T DE 69602946T DE 69602946 T DE69602946 T DE 69602946T DE 69602946 D1 DE69602946 D1 DE 69602946D1
- Authority
- DE
- Germany
- Prior art keywords
- pipeline
- operating
- storage system
- addressed storage
- addressed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/502,479 US5598374A (en) | 1995-07-14 | 1995-07-14 | Pipeland address memories, and systems and methods using the same |
PCT/IB1996/001001 WO1997004457A2 (en) | 1995-07-14 | 1996-07-12 | Pipelined address memories, and systems and methods using the same |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69602946D1 true DE69602946D1 (de) | 1999-07-22 |
DE69602946T2 DE69602946T2 (de) | 2000-01-13 |
Family
ID=23998020
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69602946T Expired - Fee Related DE69602946T2 (de) | 1995-07-14 | 1996-07-12 | Pipelineadressiertes speichersystem und verfahren zu dessen betrieb |
Country Status (6)
Country | Link |
---|---|
US (3) | US5598374A (de) |
EP (1) | EP0839375B1 (de) |
JP (1) | JPH11509351A (de) |
KR (1) | KR19990028991A (de) |
DE (1) | DE69602946T2 (de) |
WO (1) | WO1997004457A2 (de) |
Families Citing this family (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7187572B2 (en) | 2002-06-28 | 2007-03-06 | Rambus Inc. | Early read after write operation memory device, system and method |
JP2871530B2 (ja) * | 1995-05-10 | 1999-03-17 | 日本電気株式会社 | 半導体装置の製造方法 |
JPH09161476A (ja) | 1995-10-04 | 1997-06-20 | Toshiba Corp | 半導体メモリ及びそのテスト回路、並びにデ−タ転送システム |
US5684978A (en) * | 1995-10-20 | 1997-11-04 | International Business Machines Corporation | Synchronous DRAM controller with memory access commands timed for optimized use of data bus |
JP4084428B2 (ja) * | 1996-02-02 | 2008-04-30 | 富士通株式会社 | 半導体記憶装置 |
US5815456A (en) * | 1996-06-19 | 1998-09-29 | Cirrus Logic, Inc. | Multibank -- multiport memories and systems and methods using the same |
WO1998014949A1 (de) * | 1996-09-30 | 1998-04-09 | Siemens Aktiengesellschaft | Dram |
US6075743A (en) * | 1996-12-26 | 2000-06-13 | Rambus Inc. | Method and apparatus for sharing sense amplifiers between memory banks |
US6134172A (en) * | 1996-12-26 | 2000-10-17 | Rambus Inc. | Apparatus for sharing sense amplifiers between memory banks |
US5815697A (en) * | 1997-01-09 | 1998-09-29 | Texas Instruments Incorporated | Circuits, systems, and methods for reducing microprogram memory power for multiway branching |
JPH10283770A (ja) * | 1997-04-07 | 1998-10-23 | Oki Electric Ind Co Ltd | 半導体メモリ装置およびその読み出しおよび書き込み方法 |
US5881016A (en) * | 1997-06-13 | 1999-03-09 | Cirrus Logic, Inc. | Method and apparatus for optimizing power consumption and memory bandwidth in a video controller using SGRAM and SDRAM power reduction modes |
US6026466A (en) * | 1997-06-16 | 2000-02-15 | Integrated Silicon Solution, Inc. | Multiple row address strobe DRAM architecture to improve bandwidth |
US6067255A (en) * | 1997-07-03 | 2000-05-23 | Samsung Electronics Co., Ltd. | Merged memory and logic (MML) integrated circuits including independent memory bank signals and methods |
US6009522A (en) * | 1997-09-30 | 1999-12-28 | Micron Electronics, Inc. | Attachment or integration of a BIOS device into a computer system using the system memory data bus |
US6003103A (en) * | 1997-09-30 | 1999-12-14 | Micron Electronics, Inc. | Method for attachment or integration of a bios device into a computer system using a local bus |
US6182213B1 (en) | 1997-09-30 | 2001-01-30 | Micron Electronics, Inc. | Method for attachment of a bios device into a computer system using the system memory data bus |
US6076118A (en) * | 1997-09-30 | 2000-06-13 | Micron Electronics, Inc. | Attachment or integration of a BIOS device into a computer system using the system memory address and data bus |
US5889714A (en) * | 1997-11-03 | 1999-03-30 | Digital Equipment Corporation | Adaptive precharge management for synchronous DRAM |
US5870325A (en) * | 1998-04-14 | 1999-02-09 | Silicon Graphics, Inc. | Memory system with multiple addressing and control busses |
US6526471B1 (en) * | 1998-09-18 | 2003-02-25 | Digeo, Inc. | Method and apparatus for a high-speed memory subsystem |
US20020124195A1 (en) * | 1998-11-04 | 2002-09-05 | Puthiya K. Nizar | Method and apparatus for power management in a memory subsystem |
US6314049B1 (en) * | 2000-03-30 | 2001-11-06 | Micron Technology, Inc. | Elimination of precharge operation in synchronous flash memory |
KR100872213B1 (ko) | 2000-07-07 | 2008-12-05 | 모사이드 테크놀로지스, 인코포레이티드 | 메모리 소자에서의 읽기 명령 수행 방법 |
KR100443910B1 (ko) * | 2001-12-17 | 2004-08-09 | 삼성전자주식회사 | 반도체 메모리 장치 및 이 장치의 메모리 셀 억세스 방법 |
US6769047B2 (en) * | 2002-03-21 | 2004-07-27 | Intel Corporation | Method and system for maximizing DRAM memory bandwidth through storing memory bank indexes in associated buffers |
KR100535131B1 (ko) * | 2003-05-30 | 2005-12-07 | 주식회사 하이닉스반도체 | 페이지 모드에서의 메모리 소자 리드 방법 및 이를 이용한로우 디코더 제어회로 |
US11948629B2 (en) | 2005-09-30 | 2024-04-02 | Mosaid Technologies Incorporated | Non-volatile memory device with concurrent bank operations |
TWI446356B (zh) | 2005-09-30 | 2014-07-21 | Mosaid Technologies Inc | 具有輸出控制之記憶體及其系統 |
US7652922B2 (en) * | 2005-09-30 | 2010-01-26 | Mosaid Technologies Incorporated | Multiple independent serial link memory |
US7755961B2 (en) * | 2006-07-07 | 2010-07-13 | Rao G R Mohan | Memories with selective precharge |
US7724593B2 (en) * | 2006-07-07 | 2010-05-25 | Rao G R Mohan | Memories with front end precharge |
KR101088548B1 (ko) * | 2006-07-07 | 2011-12-05 | 에스. 아쿠아 세미컨덕터 엘엘씨 | 전단 프리차지를 하는 메모리 |
SG143078A1 (en) * | 2006-11-13 | 2008-06-27 | Singapore Tech Dynamics Pte | Diversion of sailing vessel by tethering method and apparatus therefor with harpoon means |
US7995409B2 (en) * | 2007-10-16 | 2011-08-09 | S. Aqua Semiconductor, Llc | Memory with independent access and precharge |
US8095853B2 (en) | 2007-10-19 | 2012-01-10 | S. Aqua Semiconductor Llc | Digital memory with fine grain write operation |
KR100932095B1 (ko) * | 2009-06-30 | 2009-12-16 | 주식회사 셀픽 | 다중 스트로브를 이용한 플래시 메모리 시스템 및 그 제어 방법 |
US10373665B2 (en) * | 2016-03-10 | 2019-08-06 | Micron Technology, Inc. | Parallel access techniques within memory sections through section independence |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR960003526B1 (ko) * | 1992-10-02 | 1996-03-14 | 삼성전자주식회사 | 반도체 메모리장치 |
JPS5873096A (ja) * | 1981-10-27 | 1983-05-02 | Nec Corp | 半導体メモリ |
JPS60108953A (ja) * | 1983-11-15 | 1985-06-14 | モトローラ・インコーポレーテツド | メモリデータバスの多重化方法 |
US4754425A (en) * | 1985-10-18 | 1988-06-28 | Gte Communication Systems Corporation | Dynamic random access memory refresh circuit selectively adapted to different clock frequencies |
US4691303A (en) * | 1985-10-31 | 1987-09-01 | Sperry Corporation | Refresh system for multi-bank semiconductor memory |
US4831594A (en) * | 1986-09-25 | 1989-05-16 | Texas Instrument, Inc. | Process and device for refreshing an array of dynamic memory cells during precharge of the column lines |
US4845677A (en) * | 1987-08-17 | 1989-07-04 | International Business Machines Corporation | Pipelined memory chip structure having improved cycle time |
JP2654548B2 (ja) * | 1987-10-02 | 1997-09-17 | 株式会社日立製作所 | 半導体記憶装置 |
US5345577A (en) * | 1989-10-13 | 1994-09-06 | Chips & Technologies, Inc. | Dram refresh controller with improved bus arbitration scheme |
JPH04149892A (ja) * | 1990-10-11 | 1992-05-22 | Fujitsu Ltd | メモリ制御方法 |
US5159572A (en) * | 1990-12-24 | 1992-10-27 | Motorola, Inc. | DRAM architecture having distributed address decoding and timing control |
US5265231A (en) * | 1991-02-08 | 1993-11-23 | Thinking Machines Corporation | Refresh control arrangement and a method for refreshing a plurality of random access memory banks in a memory system |
JP2999869B2 (ja) * | 1991-11-15 | 2000-01-17 | 沖電気工業株式会社 | メモリアクセス方式 |
JPH05266657A (ja) * | 1992-03-23 | 1993-10-15 | Nec Corp | ダイナミック型半導体メモリ |
JPH0729376A (ja) * | 1993-07-14 | 1995-01-31 | Ricoh Co Ltd | 半導体メモリ装置及びデータ読み書き方法 |
KR960006271B1 (ko) * | 1993-08-14 | 1996-05-13 | 삼성전자주식회사 | 고속동작을 위한 입출력라인구동방식을 가지는 반도체메모리장치 |
KR100230230B1 (ko) * | 1993-12-24 | 1999-11-15 | 윤종용 | 메모리 어드레싱 방법 및 장치 |
US5506810A (en) * | 1994-08-16 | 1996-04-09 | Cirrus Logic, Inc. | Dual bank memory and systems using the same |
US5619464A (en) * | 1995-06-07 | 1997-04-08 | Advanced Micro Devices, Inc. | High performance RAM array circuit employing self-time clock generator for enabling array accessess |
-
1995
- 1995-07-14 US US08/502,479 patent/US5598374A/en not_active Expired - Lifetime
-
1996
- 1996-06-14 US US08/666,683 patent/US5657285A/en not_active Expired - Lifetime
- 1996-06-14 US US08/664,471 patent/US5745428A/en not_active Expired - Lifetime
- 1996-07-12 JP JP9506502A patent/JPH11509351A/ja active Pending
- 1996-07-12 DE DE69602946T patent/DE69602946T2/de not_active Expired - Fee Related
- 1996-07-12 EP EP96930308A patent/EP0839375B1/de not_active Expired - Lifetime
- 1996-07-12 WO PCT/IB1996/001001 patent/WO1997004457A2/en not_active Application Discontinuation
- 1996-07-12 KR KR1019980700293A patent/KR19990028991A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
DE69602946T2 (de) | 2000-01-13 |
WO1997004457A3 (en) | 1997-03-06 |
JPH11509351A (ja) | 1999-08-17 |
US5657285A (en) | 1997-08-12 |
KR19990028991A (ko) | 1999-04-15 |
WO1997004457A2 (en) | 1997-02-06 |
EP0839375B1 (de) | 1999-06-16 |
EP0839375A2 (de) | 1998-05-06 |
US5745428A (en) | 1998-04-28 |
US5598374A (en) | 1997-01-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |