DE69534412D1 - III-V-Halbleiterstruktur und Verfahren zu deren Herstellung - Google Patents
III-V-Halbleiterstruktur und Verfahren zu deren HerstellungInfo
- Publication number
- DE69534412D1 DE69534412D1 DE69534412T DE69534412T DE69534412D1 DE 69534412 D1 DE69534412 D1 DE 69534412D1 DE 69534412 T DE69534412 T DE 69534412T DE 69534412 T DE69534412 T DE 69534412T DE 69534412 D1 DE69534412 D1 DE 69534412D1
- Authority
- DE
- Germany
- Prior art keywords
- iii
- production
- semiconductor structure
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
- H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
- H01L29/66863—Lateral single gate transistors
- H01L29/66878—Processes wherein the final gate is made before the formation, e.g. activation anneal, of the source and drain regions in the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US254209 | 1994-06-06 | ||
US08/254,209 US5512518A (en) | 1994-06-06 | 1994-06-06 | Method of manufacture of multilayer dielectric on a III-V substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69534412D1 true DE69534412D1 (de) | 2005-10-06 |
DE69534412T2 DE69534412T2 (de) | 2006-03-09 |
Family
ID=22963356
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69534412T Expired - Lifetime DE69534412T2 (de) | 1994-06-06 | 1995-05-29 | III-V-Halbleiterstruktur und Verfahren zu deren Herstellung |
Country Status (6)
Country | Link |
---|---|
US (1) | US5512518A (de) |
EP (1) | EP0688044B1 (de) |
JP (2) | JP3621752B2 (de) |
KR (1) | KR100355691B1 (de) |
CN (1) | CN1086511C (de) |
DE (1) | DE69534412T2 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5830774A (en) * | 1996-06-24 | 1998-11-03 | Motorola, Inc. | Method for forming a metal pattern on a substrate |
US5821170A (en) * | 1996-09-30 | 1998-10-13 | Motorola, Inc. | Method for etching an insulating material |
US5966624A (en) * | 1997-07-29 | 1999-10-12 | Siemens Aktiengesellschaft | Method of manufacturing a semiconductor structure having a crystalline layer |
US6156665A (en) * | 1998-04-13 | 2000-12-05 | Lucent Technologies Inc. | Trilayer lift-off process for semiconductor device metallization |
US6528405B1 (en) | 2000-02-18 | 2003-03-04 | Motorola, Inc. | Enhancement mode RF device and fabrication method |
US6821829B1 (en) * | 2000-06-12 | 2004-11-23 | Freescale Semiconductor, Inc. | Method of manufacturing a semiconductor component and semiconductor component thereof |
US7504677B2 (en) * | 2005-03-28 | 2009-03-17 | Freescale Semiconductor, Inc. | Multi-gate enhancement mode RF switch and bias arrangement |
JP4799965B2 (ja) * | 2005-09-06 | 2011-10-26 | 日本電信電話株式会社 | 窒化物半導体を用いたヘテロ構造電界効果トランジスタ |
US7834456B2 (en) * | 2009-01-20 | 2010-11-16 | Raytheon Company | Electrical contacts for CMOS devices and III-V devices formed on a silicon substrate |
US8357571B2 (en) * | 2010-09-10 | 2013-01-22 | Cree, Inc. | Methods of forming semiconductor contacts |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3798752A (en) * | 1971-03-11 | 1974-03-26 | Nippon Electric Co | Method of producing a silicon gate insulated-gate field effect transistor |
US3903591A (en) * | 1971-09-22 | 1975-09-09 | Siemens Ag | Semiconductor arrangement |
US3925572A (en) * | 1972-10-12 | 1975-12-09 | Ncr Co | Multilevel conductor structure and method |
US3978577A (en) * | 1975-06-30 | 1976-09-07 | International Business Machines Corporation | Fixed and variable threshold N-channel MNOSFET integration technique |
DE2967538D1 (en) * | 1978-06-14 | 1985-12-05 | Fujitsu Ltd | Process for producing a semiconductor device having an insulating layer of silicon dioxide covered by a film of silicon oxynitride |
JPS59106172A (ja) * | 1982-12-07 | 1984-06-19 | インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン | 電界効果トランジスタの製造方法 |
JPS60136267A (ja) * | 1983-12-23 | 1985-07-19 | Fujitsu Ltd | 半導体装置の製造方法 |
US4656101A (en) * | 1984-11-07 | 1987-04-07 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device with a protective film |
US4789648A (en) * | 1985-10-28 | 1988-12-06 | International Business Machines Corporation | Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias |
US4944836A (en) * | 1985-10-28 | 1990-07-31 | International Business Machines Corporation | Chem-mech polishing method for producing coplanar metal/insulator films on a substrate |
US4767724A (en) * | 1986-03-27 | 1988-08-30 | General Electric Company | Unframed via interconnection with dielectric etch stop |
JPS62272571A (ja) * | 1986-05-21 | 1987-11-26 | Hitachi Ltd | 半導体装置 |
JPS62276832A (ja) * | 1986-05-26 | 1987-12-01 | Hitachi Ltd | 被膜形成方法およびそれを用いた半導体装置の製造方法 |
JPH01244666A (ja) * | 1988-03-25 | 1989-09-29 | Nec Corp | 半導体装置の製造方法 |
JPH03124025A (ja) * | 1989-10-06 | 1991-05-27 | Nec Corp | 半導体装置の製造方法 |
JPH03265586A (ja) * | 1990-03-15 | 1991-11-26 | Toshiba Corp | 窒化アルミニウム基板の製造方法 |
JP2762800B2 (ja) * | 1991-10-15 | 1998-06-04 | 日本電気株式会社 | 量子細線構造の製造方法 |
US5350709A (en) * | 1992-06-13 | 1994-09-27 | Sanyo Electric Co., Ltd. | Method of doping a group III-V compound semiconductor |
-
1994
- 1994-06-06 US US08/254,209 patent/US5512518A/en not_active Expired - Lifetime
-
1995
- 1995-05-26 KR KR1019950013374A patent/KR100355691B1/ko not_active IP Right Cessation
- 1995-05-29 DE DE69534412T patent/DE69534412T2/de not_active Expired - Lifetime
- 1995-05-29 EP EP95108175A patent/EP0688044B1/de not_active Expired - Lifetime
- 1995-05-29 JP JP15274895A patent/JP3621752B2/ja not_active Expired - Fee Related
- 1995-06-05 CN CN95106587A patent/CN1086511C/zh not_active Expired - Lifetime
-
2004
- 2004-09-27 JP JP2004279032A patent/JP2005051265A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
DE69534412T2 (de) | 2006-03-09 |
KR960002524A (ko) | 1996-01-26 |
JPH07335675A (ja) | 1995-12-22 |
CN1113606A (zh) | 1995-12-20 |
EP0688044A2 (de) | 1995-12-20 |
EP0688044A3 (de) | 1997-12-29 |
CN1086511C (zh) | 2002-06-19 |
KR100355691B1 (ko) | 2002-12-11 |
JP2005051265A (ja) | 2005-02-24 |
US5512518A (en) | 1996-04-30 |
EP0688044B1 (de) | 2005-08-31 |
JP3621752B2 (ja) | 2005-02-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |