DE69524315D1 - Speicherarchitektur für eine automatische Testeinrichtung mit Vektormodultabelle - Google Patents

Speicherarchitektur für eine automatische Testeinrichtung mit Vektormodultabelle

Info

Publication number
DE69524315D1
DE69524315D1 DE69524315T DE69524315T DE69524315D1 DE 69524315 D1 DE69524315 D1 DE 69524315D1 DE 69524315 T DE69524315 T DE 69524315T DE 69524315 T DE69524315 T DE 69524315T DE 69524315 D1 DE69524315 D1 DE 69524315D1
Authority
DE
Germany
Prior art keywords
modules
memory
test device
automatic test
memory architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69524315T
Other languages
English (en)
Other versions
DE69524315T2 (de
Inventor
Peter A Reichert
Benjamin J Brown
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teradyne Inc
Original Assignee
Teradyne Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teradyne Inc filed Critical Teradyne Inc
Application granted granted Critical
Publication of DE69524315D1 publication Critical patent/DE69524315D1/de
Publication of DE69524315T2 publication Critical patent/DE69524315T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919—Storing and outputting test patterns
    • G01R31/31921—Storing and outputting test patterns using compression techniques, e.g. patterns sequencer

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE69524315T 1994-09-01 1995-09-01 Speicherarchitektur für eine automatische Testeinrichtung mit Vektormodultabelle Expired - Fee Related DE69524315T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/299,753 US6286120B1 (en) 1994-09-01 1994-09-01 Memory architecture for automatic test equipment using vector module table

Publications (2)

Publication Number Publication Date
DE69524315D1 true DE69524315D1 (de) 2002-01-17
DE69524315T2 DE69524315T2 (de) 2002-08-08

Family

ID=23156144

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69524315T Expired - Fee Related DE69524315T2 (de) 1994-09-01 1995-09-01 Speicherarchitektur für eine automatische Testeinrichtung mit Vektormodultabelle

Country Status (4)

Country Link
US (1) US6286120B1 (de)
EP (1) EP0699999B1 (de)
KR (1) KR100351768B1 (de)
DE (1) DE69524315T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6014764A (en) * 1997-05-20 2000-01-11 Schlumberger Technologies Inc. Providing test vectors with pattern chaining definition
US6389525B1 (en) * 1999-01-08 2002-05-14 Teradyne, Inc. Pattern generator for a packet-based memory tester
US6651203B1 (en) 1999-05-17 2003-11-18 Infineon Technologies Ag On chip programmable data pattern generator for semiconductor memories
JP2002131395A (ja) * 2000-10-18 2002-05-09 Ando Electric Co Ltd 半導体試験装置及びその制御方法
US6836868B1 (en) * 2000-10-31 2004-12-28 Credence Systems Corporation High-speed algorithmic pattern generator
KR20050007474A (ko) * 2002-05-08 2005-01-18 엔피테스트, 인코포레이티드 다목적 메모리를 지닌 테스터 시스템
JP2005524851A (ja) * 2002-05-08 2005-08-18 エヌピーテスト， インコーポレイテッド 複数の命令メモリを有するテスタシステム
US7117410B2 (en) 2002-12-20 2006-10-03 Teradyne, Inc. Distributed failure analysis memory for automatic test equipment
KR20040101660A (ko) * 2003-05-26 2004-12-03 삼성전자주식회사 테스트용 신호 패스를 가지는 출력 버퍼 회로 및 이에대한 테스트 방법
CN105092992B (zh) * 2014-04-15 2020-01-07 爱德万测试公司 用于在ate上进行向量控制的测试的方法和设备
JP6386434B2 (ja) * 2015-10-08 2018-09-05 株式会社アドバンテスト 試験装置、試験信号供給装置、試験方法、およびプログラム
US10438682B2 (en) 2017-12-21 2019-10-08 International Business Machines Corporation List insertion in test segments with non-naturally aligned data boundaries

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52144125A (en) 1976-05-26 1977-12-01 Japan National Railway Tunnel
JPS5476041A (en) 1977-11-30 1979-06-18 Nec Corp Test pattern generator for logic circuit
US4313200A (en) * 1978-08-28 1982-01-26 Takeda Riken Kogyo Kabushikikaisha Logic test system permitting test pattern changes without dummy cycles
US4451918A (en) 1981-10-09 1984-05-29 Teradyne, Inc. Test signal reloader
US4502127A (en) 1982-05-17 1985-02-26 Fairchild Camera And Instrument Corporation Test system memory architecture for passing parameters and testing dynamic components
US4994732A (en) 1985-12-18 1991-02-19 Schlumberger Technologies, Inc. Automatic test system having a "true tester-per-pin" architecture
US4875210A (en) 1988-01-06 1989-10-17 Teradyne, Inc. Automatic circuit tester control system
US5179667A (en) * 1988-09-14 1993-01-12 Silicon Graphics, Inc. Synchronized DRAM control apparatus using two different clock rates
DE69029122T2 (de) 1989-06-16 1997-04-03 Advantest Corp Prüfmustergenerator
US5122988A (en) 1989-09-21 1992-06-16 Schlumberger Tecnologies, Inc. Data stream smoothing using a FIFO memory
US5151903A (en) 1989-09-28 1992-09-29 Texas Instruments Incorporated High efficiency pattern sequence controller for automatic test equipment
US5270582A (en) 1989-10-11 1993-12-14 Teradyne, Inc. High speed timing generator
JP3225531B2 (ja) * 1990-05-15 2001-11-05 セイコーエプソン株式会社 メモリカード
JP2602997B2 (ja) 1991-01-18 1997-04-23 株式会社東芝 パターン発生器
US5379400A (en) * 1992-08-07 1995-01-03 International Business Machines Corp. Method and system for determining memory refresh rate

Also Published As

Publication number Publication date
EP0699999B1 (de) 2001-12-05
DE69524315T2 (de) 2002-08-08
KR960011442A (ko) 1996-04-20
EP0699999A2 (de) 1996-03-06
EP0699999A3 (de) 1996-11-27
US6286120B1 (en) 2001-09-04
KR100351768B1 (ko) 2002-12-31

Similar Documents

Publication Publication Date Title
DE69524315D1 (de) Speicherarchitektur für eine automatische Testeinrichtung mit Vektormodultabelle
DE69114183D1 (de) System zur Reduzierung von Prüfdatenspeichern.
KR920008768A (ko) 반도체기억장치
KR970051182A (ko) 반도체 기억 장치
TW324823B (en) Cross-coupled bitline segments for generalized data propagation
KR960042769A (ko) 치환 전에 액세스 가능한 용장행 및 용장열을 갖는 반도체기억장치
EP0547682A3 (de)
CA2007312A1 (en) Parallel time slot interchanger matrix and switch block module for use therewith
KR870700140A (ko) 테스트 패턴 제너레이터(발생장치)
DE69909926D1 (de) Nichtflüchtige Speicheranordnung und Verfahren zu ihrer Prüfung
DE69220256D1 (de) Halbleiterspeicheranordnung
KR960019313A (ko) 반도체 메모리 장치
DE69321623D1 (de) Redundanzspeicherzellen mit Parallelprüffunktion enthaltendes Halbleiter-Speichergerät
TW332355B (en) Semiconductor device having a latch circuit for latching externally input data
KR100200692B1 (ko) 반도체 메모리장치의 시분할 워드라인 구동회로
DE69629430D1 (de) Austausch-Halbleiterfestwertspeicher
EP0566153A3 (en) Semiconductor memory device having test mode
DE69712818D1 (de) Halbleiterspeicheranordnung
GR3018555T3 (en) Switch with a circuit arrangement for testing the speech path interconnection of a coupling device
KR910020722A (ko) 집적 반도체 메모리
KR960019298A (ko) 반도체 소자의 신호 변환장치
KR960043827A (ko) 선국장치
JPS6439039A (en) Semiconductor integrated circuit device with gate array and memory
KR970051218A (ko) 반도체 메모리 장치의 대기전류 검출회로
KR19990043091A (ko) 입력 전압 제어 장치

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee