DE69503205D1 - Cmos eingang mit vcc-kompensierter dynamischer schwelle - Google Patents

Cmos eingang mit vcc-kompensierter dynamischer schwelle

Info

Publication number
DE69503205D1
DE69503205D1 DE69503205T DE69503205T DE69503205D1 DE 69503205 D1 DE69503205 D1 DE 69503205D1 DE 69503205 T DE69503205 T DE 69503205T DE 69503205 T DE69503205 T DE 69503205T DE 69503205 D1 DE69503205 D1 DE 69503205D1
Authority
DE
Germany
Prior art keywords
vcc
dynamic threshold
cmos input
compensated dynamic
compensated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69503205T
Other languages
English (en)
Other versions
DE69503205T2 (de
Inventor
Brian Martin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Electronics NV
Philips Norden AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV, Philips Norden AB filed Critical Philips Electronics NV
Publication of DE69503205D1 publication Critical patent/DE69503205D1/de
Application granted granted Critical
Publication of DE69503205T2 publication Critical patent/DE69503205T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
DE69503205T 1994-03-25 1995-03-17 Cmos eingang mit vcc-kompensierter dynamischer schwelle Expired - Fee Related DE69503205T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US21848194A 1994-03-25 1994-03-25
PCT/IB1995/000183 WO1995026590A1 (en) 1994-03-25 1995-03-17 Cmos input with vcc compensated dynamic threshold

Publications (2)

Publication Number Publication Date
DE69503205D1 true DE69503205D1 (de) 1998-08-06
DE69503205T2 DE69503205T2 (de) 1999-02-11

Family

ID=22815291

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69503205T Expired - Fee Related DE69503205T2 (de) 1994-03-25 1995-03-17 Cmos eingang mit vcc-kompensierter dynamischer schwelle

Country Status (6)

Country Link
US (1) US5495187A (de)
EP (1) EP0700599B1 (de)
JP (1) JP3586467B2 (de)
KR (1) KR100365605B1 (de)
DE (1) DE69503205T2 (de)
WO (1) WO1995026590A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2896305B2 (ja) * 1993-05-15 1999-05-31 株式会社東芝 半導体集積回路装置
US5532617A (en) * 1994-03-25 1996-07-02 Philips Electronics North America Corporation CMOS input with temperature and VCC compensated threshold
US5668488A (en) * 1994-11-17 1997-09-16 Advanced Micro Devices, Inc. Input buffer for a high density programmable logic device
US5739713A (en) * 1995-12-19 1998-04-14 Advanced Micro Devices, Inc. Deconvolution input buffer compensating for capacitance of a switch matrix of a high density programmable logic device
US5744982A (en) * 1996-04-22 1998-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Input buffer circuit
US6147513A (en) * 1998-05-01 2000-11-14 Winbond Electronics Corporation Method and circuit for logic input buffer
WO2003075464A1 (en) * 2002-03-06 2003-09-12 Igor Anatolievich Abrosimov Line driver with reduced power consumption
US7203243B2 (en) * 2003-03-10 2007-04-10 Acuid Corporation (Guernsey) Limited Line driver with reduced power consumption
WO2015045207A1 (ja) * 2013-09-27 2015-04-02 パナソニック株式会社 半導体集積回路および半導体集積回路装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5859628A (ja) * 1981-09-03 1983-04-08 Toshiba Corp Ｍｏｓ形論理回路
US4533841A (en) * 1981-09-03 1985-08-06 Tokyo Shibaura Denki Kabushiki Kaisha MOS logic circuit responsive to an irreversible control voltage for permanently varying its signal transfer characteristic
US4477741A (en) * 1982-03-29 1984-10-16 International Business Machines Corporation Dynamic output impedance for 3-state drivers
US4553043A (en) * 1983-03-28 1985-11-12 Codex Corporation High speed drive circuit
JPS644152A (en) * 1987-06-26 1989-01-09 Nec Corp Cpu controlled type subscriber line control interface circuit
JP2542678B2 (ja) * 1988-06-17 1996-10-09 富士通株式会社 半導体装置
KR910005609B1 (ko) * 1988-07-19 1991-07-31 삼성전자 주식회사 복수전압 ic용 입력신호 로직 판별회로
JPH0270120A (ja) * 1988-09-05 1990-03-09 Nec Corp 出力回路
JPH02161817A (ja) * 1988-12-14 1990-06-21 Nec Corp インバーター回路
US4958089A (en) * 1988-12-20 1990-09-18 Gazelle Microcircuits, Inc. High output drive FET buffer for providing high initial current to a subsequent stage
US4933574A (en) * 1989-01-30 1990-06-12 Integrated Device Technology, Inc. BiCMOS output driver
US4999529A (en) * 1989-06-30 1991-03-12 At&T Bell Laboratories Programmable logic level input buffer
JPH0793565B2 (ja) * 1989-11-09 1995-10-09 日本電気株式会社 レベル変換回路
US5128555A (en) * 1991-03-18 1992-07-07 Motorola, Inc. Pulsed CMOS logic circuit having selectable rise and fall times
JP2758735B2 (ja) * 1991-06-26 1998-05-28 日本電気アイシーマイコンシステム株式会社 論理回路
US5258665A (en) * 1992-05-12 1993-11-02 National Semiconductor Corporation AC Miller-Killer circuit for L→Z transitions
US5341045A (en) * 1992-11-06 1994-08-23 Intel Corporation Programmable input buffer

Also Published As

Publication number Publication date
EP0700599B1 (de) 1998-07-01
KR960702698A (ko) 1996-04-27
US5495187A (en) 1996-02-27
EP0700599A1 (de) 1996-03-13
JPH08511399A (ja) 1996-11-26
JP3586467B2 (ja) 2004-11-10
DE69503205T2 (de) 1999-02-11
KR100365605B1 (ko) 2003-03-15
WO1995026590A1 (en) 1995-10-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8339 Ceased/non-payment of the annual fee