DE69430461T2 - Neue Verbindungstechnik in bedeckten TiSi2/TiN - Google Patents

Neue Verbindungstechnik in bedeckten TiSi2/TiN

Info

Publication number
DE69430461T2
DE69430461T2 DE69430461T DE69430461T DE69430461T2 DE 69430461 T2 DE69430461 T2 DE 69430461T2 DE 69430461 T DE69430461 T DE 69430461T DE 69430461 T DE69430461 T DE 69430461T DE 69430461 T2 DE69430461 T2 DE 69430461T2
Authority
DE
Germany
Prior art keywords
titanium
layer
tin
zones
tisi2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69430461T
Other languages
German (de)
English (en)
Other versions
DE69430461D1 (de
Inventor
Shin-Puu Jeng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69430461D1 publication Critical patent/DE69430461D1/de
Application granted granted Critical
Publication of DE69430461T2 publication Critical patent/DE69430461T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0107Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/915Active solid-state devices, e.g. transistors, solid-state diodes with titanium nitride portion or region

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69430461T 1993-01-12 1994-01-11 Neue Verbindungstechnik in bedeckten TiSi2/TiN Expired - Fee Related DE69430461T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US320993A 1993-01-12 1993-01-12

Publications (2)

Publication Number Publication Date
DE69430461D1 DE69430461D1 (de) 2002-05-29
DE69430461T2 true DE69430461T2 (de) 2002-11-14

Family

ID=21704729

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69430461T Expired - Fee Related DE69430461T2 (de) 1993-01-12 1994-01-11 Neue Verbindungstechnik in bedeckten TiSi2/TiN

Country Status (6)

Country Link
US (1) US5936306A (enExample)
EP (1) EP0638930B1 (enExample)
JP (1) JPH077095A (enExample)
KR (1) KR100309857B1 (enExample)
DE (1) DE69430461T2 (enExample)
TW (1) TW270226B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990067331A (ko) * 1995-11-06 1999-08-16 야스카와 히데아키 국소 배선부를 포함하는 반도체 장치 및 그 제조 방법
US6391760B1 (en) * 1998-12-08 2002-05-21 United Microelectronics Corp. Method of fabricating local interconnect
US6737716B1 (en) * 1999-01-29 2004-05-18 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6495413B2 (en) 2001-02-28 2002-12-17 Ramtron International Corporation Structure for masking integrated capacitors of particular utility for ferroelectric memory integrated circuits
US6423592B1 (en) 2001-06-26 2002-07-23 Ramtron International Corporation PZT layer as a temporary encapsulation and hard mask for a ferroelectric capacitor
US6534807B2 (en) 2001-08-13 2003-03-18 International Business Machines Corporation Local interconnect junction on insulator (JOI) structure
US7479437B2 (en) * 2006-04-28 2009-01-20 International Business Machines Corporation Method to reduce contact resistance on thin silicon-on-insulator device
KR101641347B1 (ko) 2014-12-15 2016-07-21 피앤씨테크 주식회사 환기 팬 및 가스 차단기 제어 시스템 및 방법
KR20230158772A (ko) 2022-05-12 2023-11-21 (주)엘엑스하우시스 조리 상황 인지 장치 및 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3777364A (en) * 1972-07-31 1973-12-11 Fairchild Camera Instr Co Methods for forming metal/metal silicide semiconductor device interconnect system
US4804636A (en) * 1985-05-01 1989-02-14 Texas Instruments Incorporated Process for making integrated circuits having titanium nitride triple interconnect
US4975756A (en) * 1985-05-01 1990-12-04 Texas Instruments Incorporated SRAM with local interconnect
US4814854A (en) * 1985-05-01 1989-03-21 Texas Instruments Incorporated Integrated circuit device and process with tin-gate transistor
US4746219A (en) * 1986-03-07 1988-05-24 Texas Instruments Incorporated Local interconnect
JPS6358943A (ja) * 1986-08-29 1988-03-14 Mitsubishi Electric Corp 電極・配線膜の構造
US4782380A (en) * 1987-01-22 1988-11-01 Advanced Micro Devices, Inc. Multilayer interconnection for integrated circuit structure having two or more conductive metal layers
US4962414A (en) * 1988-02-11 1990-10-09 Sgs-Thomson Microelectronics, Inc. Method for forming a contact VIA
US5168076A (en) * 1990-01-12 1992-12-01 Paradigm Technology, Inc. Method of fabricating a high resistance polysilicon load resistor
FR2658951B1 (fr) * 1990-02-23 1992-05-07 Bonis Maurice Procede de fabrication d'un circuit integre pour filiere analogique rapide utilisant des lignes d'interconnexions locales en siliciure.
US5091763A (en) * 1990-12-19 1992-02-25 Intel Corporation Self-aligned overlap MOSFET and method of fabrication
EP0517368B1 (en) * 1991-05-03 1998-09-16 STMicroelectronics, Inc. Local interconnect for integrated circuits
US5173450A (en) * 1991-12-30 1992-12-22 Texas Instruments Incorporated Titanium silicide local interconnect process

Also Published As

Publication number Publication date
TW270226B (enExample) 1996-02-11
DE69430461D1 (de) 2002-05-29
EP0638930A1 (en) 1995-02-15
US5936306A (en) 1999-08-10
KR940018699A (ko) 1994-08-18
JPH077095A (ja) 1995-01-10
EP0638930B1 (en) 2002-04-24
KR100309857B1 (ko) 2003-07-16

Similar Documents

Publication Publication Date Title
DE69226987T2 (de) Lokalverbindungen für integrierte Schaltungen
EP0600063B2 (de) Verfahren zur herstellung von halbleiterbauelementen in cmos-technik mit 'local interconnects'
DE2951734C2 (enExample)
US5654575A (en) TiSi2 /TiN clad interconnect technology
DE3211761C2 (enExample)
DE69229983T2 (de) Halbleiterschaltung mit einem Kontakt mit niedrigem Widerstand und ihr Herstellungsverfahren
DE69429951T2 (de) Herstellungsverfahren für Halbleiteranordnung unter Verwendung der selektiven CVD-Methode
DE3750325T2 (de) Verfahren zum Herstellen eines Halbleiterbauelements.
DE68926440T2 (de) Verfahren zur Selektivabscheidung von refraktorischen Metallen auf Siliziumkörpern
DE69031447T2 (de) Verfahren zur Herstellung von MIS-Halbleiterbauelementen
DE69226098T2 (de) Lokale Kontaktverbindungen für integrierte Schaltungen
DE69123884T2 (de) Verfahren und Struktur zur Verbindung von verschiedenen Zonen aus Polysilizium für integrierte Schaltkreise
DE3901114A1 (de) Verfahren zur herstellung einer halbleitervorrichtung
DE69319867T2 (de) Verfahren zur herstellung einer lokalen verbindung und eines hohen polisiliziumwiderstands
DE4010618A1 (de) Halbleitervorrichtung und verfahren zu ihrer herstellung
DE69430461T2 (de) Neue Verbindungstechnik in bedeckten TiSi2/TiN
DE3122437A1 (de) Verfahren zum herstellen eines mos-bauelements
DE19723062C2 (de) Verfahren zum Bilden einer selbst ausgerichteten Metallverdrahtung für ein Halbleiterbauelement
DE69317012T2 (de) Herstellungsverfahren einer Verbindungsstruktur in einer integrierten Schaltung
DE69420805T2 (de) Herstellungsverfahren für Kontakte in dem Speichergebiet und dem Randgebiet eines IC
DE69029046T2 (de) Kontakte für Halbleiter-Vorrichtungen
DE19531602C2 (de) Verbindungsstruktur einer Halbleitereinrichtung und ihr Herstellungsverfahren
DE69227150T2 (de) Verfahren zur Herstellung einer Halbleiteranordnung mit einer isolierenden Seitenwand
DE19608883C2 (de) Herstellungsverfahren für eine Halbleitervorrichtung und dadurch hergestellte Halbleitervorrichtung
DE4329260B4 (de) Verfahren zur Herstellung einer Verdrahtung in einem Halbleiterbauelement

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee