DE69425733D1 - Anordnung und verfahren zur reduzierung der auswirkungen des thermischen zyklus in einer halbleiterpackung - Google Patents

Anordnung und verfahren zur reduzierung der auswirkungen des thermischen zyklus in einer halbleiterpackung

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Publication number
DE69425733D1
DE69425733D1 DE69425733T DE69425733T DE69425733D1 DE 69425733 D1 DE69425733 D1 DE 69425733D1 DE 69425733 T DE69425733 T DE 69425733T DE 69425733 T DE69425733 T DE 69425733T DE 69425733 D1 DE69425733 D1 DE 69425733D1
Authority
DE
Germany
Prior art keywords
arrangement
reducing
effects
thermal cycle
pack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69425733T
Other languages
English (en)
Other versions
DE69425733T2 (de
Inventor
Peng-Cheng Lin
P Takiar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Application granted granted Critical
Publication of DE69425733D1 publication Critical patent/DE69425733D1/de
Publication of DE69425733T2 publication Critical patent/DE69425733T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3738Semiconductor materials
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    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
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    • H01L23/00Details of semiconductor or other solid state devices
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
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    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/181Encapsulation
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    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
DE69425733T 1993-03-02 1994-03-01 Anordnung und Verfahren zur Reduzierung der Auswirkung des thermischen Zyklus in einer Halbleiterpackung Expired - Fee Related DE69425733T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/025,296 US5339216A (en) 1993-03-02 1993-03-02 Device and method for reducing thermal cycling in a semiconductor package
PCT/US1994/002167 WO1994020986A1 (en) 1993-03-02 1994-03-01 Device and method for reducing thermal cycling in a semiconductor package

Publications (2)

Publication Number Publication Date
DE69425733D1 true DE69425733D1 (de) 2000-10-05
DE69425733T2 DE69425733T2 (de) 2001-04-19

Family

ID=21825192

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69425733T Expired - Fee Related DE69425733T2 (de) 1993-03-02 1994-03-01 Anordnung und Verfahren zur Reduzierung der Auswirkung des thermischen Zyklus in einer Halbleiterpackung

Country Status (5)

Country Link
US (2) US5339216A (de)
EP (1) EP0687382B1 (de)
JP (1) JPH08507656A (de)
DE (1) DE69425733T2 (de)
WO (1) WO1994020986A1 (de)

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US5339216A (en) * 1993-03-02 1994-08-16 National Semiconductor Corporation Device and method for reducing thermal cycling in a semiconductor package
US6147393A (en) * 1993-05-05 2000-11-14 Ixys Corporation Isolated multi-chip devices
JPH0758254A (ja) * 1993-08-19 1995-03-03 Fujitsu Ltd マルチチップモジュール及びその製造方法
JP3531971B2 (ja) * 1994-05-16 2004-05-31 フィガロ技研株式会社 ガスまたは湿度を検出するセンサとその製造方法
US5581444A (en) * 1995-07-26 1996-12-03 Harris Corporation Device and method for enhancing thermal and high frequency performance of integrated circuit packages
FR2771551B1 (fr) * 1997-11-21 2000-01-28 Ela Medical Sa Composant microelectromecanique, tel que microcapteur ou microactionneur, reportable sur un substrat de circuit hybride
US5969783A (en) * 1998-12-11 1999-10-19 National Semiconductor Corporation Reflective liquid crystal display and connection assembly and method
US6384890B1 (en) 1999-11-15 2002-05-07 National Semiconductor Corporation Connection assembly for reflective liquid crystal projection with branched PCB display
US6303860B1 (en) * 1999-11-30 2001-10-16 Bombardier Motor Corporation Of America Bladder insert for encapsulant displacement
US6376914B2 (en) * 1999-12-09 2002-04-23 Atmel Corporation Dual-die integrated circuit package
US6800948B1 (en) * 2002-07-19 2004-10-05 Asat Ltd. Ball grid array package
US6987032B1 (en) * 2002-07-19 2006-01-17 Asat Ltd. Ball grid array package and process for manufacturing same
US6979594B1 (en) 2002-07-19 2005-12-27 Asat Ltd. Process for manufacturing ball grid array package
TWI235469B (en) * 2003-02-07 2005-07-01 Siliconware Precision Industries Co Ltd Thermally enhanced semiconductor package with EMI shielding
US7372151B1 (en) 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
US6984785B1 (en) * 2003-10-27 2006-01-10 Asat Ltd. Thermally enhanced cavity-down integrated circuit package
US7091581B1 (en) 2004-06-14 2006-08-15 Asat Limited Integrated circuit package and process for fabricating the same
US7411289B1 (en) 2004-06-14 2008-08-12 Asat Ltd. Integrated circuit package with partially exposed contact pads and process for fabricating the same
US8610262B1 (en) 2005-02-18 2013-12-17 Utac Hong Kong Limited Ball grid array package with improved thermal characteristics
DE102005014427B4 (de) * 2005-03-24 2008-05-15 Infineon Technologies Ag Verfahren zum Verkapseln eines Halbleiterbauelements
US20070152314A1 (en) * 2005-12-30 2007-07-05 Intel Corporation Low stress stacked die packages
TWI376022B (en) * 2008-12-05 2012-11-01 Ind Tech Res Inst Semiconductor package structure and method of fabricating the same
US9355968B2 (en) * 2014-06-13 2016-05-31 Maxim Integrated Products, Inc. Silicon shield for package stress sensitive devices

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US4034469A (en) * 1976-09-03 1977-07-12 Ibm Corporation Method of making conduction-cooled circuit package
JPS60137042A (ja) * 1983-12-26 1985-07-20 Matsushita Electronics Corp 樹脂封止形半導体装置
JPS60254756A (ja) * 1984-05-31 1985-12-16 Fujitsu Ltd 樹脂封止型半導体装置およびその製造方法
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JPS6352451A (ja) * 1986-08-22 1988-03-05 Hitachi Vlsi Eng Corp レジン封止型半導体装置
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US5339216A (en) * 1993-03-02 1994-08-16 National Semiconductor Corporation Device and method for reducing thermal cycling in a semiconductor package

Also Published As

Publication number Publication date
JPH08507656A (ja) 1996-08-13
US5339216A (en) 1994-08-16
EP0687382B1 (de) 2000-08-30
US5901043A (en) 1999-05-04
EP0687382A1 (de) 1995-12-20
DE69425733T2 (de) 2001-04-19
WO1994020986A1 (en) 1994-09-15

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