DE69331358T2 - Herstellungsverfahren für eine Halbleiterwannenstruktur - Google Patents

Herstellungsverfahren für eine Halbleiterwannenstruktur

Info

Publication number
DE69331358T2
DE69331358T2 DE69331358T DE69331358T DE69331358T2 DE 69331358 T2 DE69331358 T2 DE 69331358T2 DE 69331358 T DE69331358 T DE 69331358T DE 69331358 T DE69331358 T DE 69331358T DE 69331358 T2 DE69331358 T2 DE 69331358T2
Authority
DE
Germany
Prior art keywords
manufacturing process
tub structure
semiconductor tub
semiconductor
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69331358T
Other languages
English (en)
Other versions
DE69331358D1 (de
Inventor
Mehrdad M Moslehi
John W Kuehne
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69331358D1 publication Critical patent/DE69331358D1/de
Application granted granted Critical
Publication of DE69331358T2 publication Critical patent/DE69331358T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/112—Nitridation, direct, of silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Thyristors (AREA)
DE69331358T 1992-04-16 1993-03-29 Herstellungsverfahren für eine Halbleiterwannenstruktur Expired - Fee Related DE69331358T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/869,423 US5256563A (en) 1992-04-16 1992-04-16 Doped well structure and method for semiconductor technologies

Publications (2)

Publication Number Publication Date
DE69331358D1 DE69331358D1 (de) 2002-01-31
DE69331358T2 true DE69331358T2 (de) 2002-08-14

Family

ID=25353533

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69331358T Expired - Fee Related DE69331358T2 (de) 1992-04-16 1993-03-29 Herstellungsverfahren für eine Halbleiterwannenstruktur

Country Status (6)

Country Link
US (1) US5256563A (de)
EP (1) EP0565936B1 (de)
JP (1) JPH0645543A (de)
KR (1) KR940006261A (de)
DE (1) DE69331358T2 (de)
TW (1) TW274146B (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5420056A (en) * 1994-01-14 1995-05-30 Texas Instruments Incorporated Junction contact process and structure for semiconductor technologies
US5455204A (en) * 1994-12-12 1995-10-03 International Business Machines Corporation Thin capacitor dielectric by rapid thermal processing
US5643825A (en) * 1994-12-29 1997-07-01 Advanced Micro Devices, Inc. Integrated circuit isolation process
US5583062A (en) * 1995-06-07 1996-12-10 Lsi Logic Corporation Self-aligned twin well process having a SiO2 -polysilicon-SiO2 barrier mask
KR0179831B1 (ko) * 1995-07-27 1999-03-20 문정환 반도체 소자의 웰 형성방법
US5891809A (en) * 1995-09-29 1999-04-06 Intel Corporation Manufacturable dielectric formed using multiple oxidation and anneal steps
US5679588A (en) * 1995-10-05 1997-10-21 Integrated Device Technology, Inc. Method for fabricating P-wells and N-wells having optimized field and active regions
US5776816A (en) * 1996-10-28 1998-07-07 Holtek Microelectronics, Inc. Nitride double etching for twin well align
US6110803A (en) * 1998-12-10 2000-08-29 United Microelectronics Corp. Method for fabricating a high-bias device
US8003455B2 (en) * 2009-05-21 2011-08-23 International Business Machines Corporation Implantation using a hardmask

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2199694A (en) * 1986-12-23 1988-07-13 Philips Electronic Associated A method of manufacturing a semiconductor device
US4786609A (en) * 1987-10-05 1988-11-22 North American Philips Corporation, Signetics Division Method of fabricating field-effect transistor utilizing improved gate sidewall spacers
IT1223571B (it) * 1987-12-21 1990-09-19 Sgs Thomson Microelectronics Procedimento per la fabbricazione di dispositivi integrati cmos con lunghezze di porta ridotte

Also Published As

Publication number Publication date
TW274146B (de) 1996-04-11
DE69331358D1 (de) 2002-01-31
EP0565936A1 (de) 1993-10-20
EP0565936B1 (de) 2001-12-19
US5256563A (en) 1993-10-26
KR940006261A (ko) 1994-03-23
JPH0645543A (ja) 1994-02-18

Similar Documents

Publication Publication Date Title
DE69131762D1 (de) Herstellungsverfahren für Halbleitereinrichtungen
DE59406621D1 (de) Herstellungsverfahren für vertikal kontaktierte halbleiterbauelemente
DE69428387T2 (de) Herstellungsverfahren für eine kristallisierte Halbleiterschicht
DE69333619D1 (de) Herstellungsverfahren für Halbleitersubstrate
DE69522195T2 (de) Herstellungsverfahren für Halbleiteranordnungen
DE69518793T2 (de) Herstellungsverfahren für eine Halbleitervorrichtung
DE68926033T2 (de) Herstellungsverfahren für Gross-Matrix-Halbleiterbauelemente
DE69130777T2 (de) Herstellungsverfahren für Mikrolinsen
DE68928847T2 (de) Fabrikationsverfahren für photonische, integrierte Schaltkreise
DE69133497D1 (de) Leiterrahmen für eine Halbleiteranordnung und dessen Herstellungsverfahren
DE69125208D1 (de) Trockenätzverfahren für Halbleiter
DE69131241T2 (de) Herstellungsverfahren für Halbleiteranordnungen
DE69331481D1 (de) Herstellungsverfahren für eine Halbleiter-Wannenstruktur
DE69117905T2 (de) Herstellungsverfahren für Alkoxyphthalocyanine
DE69130787T2 (de) Ätzverfahren für eine leitende Doppelschicht-Struktur
DE69401370D1 (de) Ätzverfahren für Halbleiter
DE69331358D1 (de) Herstellungsverfahren für eine Halbleiterwannenstruktur
DE69224617D1 (de) Herstellungsverfahren für einen Halbleiterlaser
DE69030433T2 (de) Herstellungsmethode für Halbleiterspeicher
DE69602791T2 (de) Herstellungsverfahren für eine Abdeckung
DE69130248D1 (de) Herstellungsverfahren für einen Halbleiterspeicher
DE69033151T2 (de) Ätzverfahren für Verbindungshalbleiter
DE69329928D1 (de) Herstellungsverfahren für integrierten Schaltkreis
DE69025916T2 (de) Herstellungsverfahren für eine halbleitervorrichtung
DE69840473D1 (de) Herstellungsverfahren für eine Halbleiterpackung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee