DE69319198D1 - Durch Schmelzsicherung programmierbare verbesserte Steuerschaltung - Google Patents

Durch Schmelzsicherung programmierbare verbesserte Steuerschaltung

Info

Publication number
DE69319198D1
DE69319198D1 DE69319198T DE69319198T DE69319198D1 DE 69319198 D1 DE69319198 D1 DE 69319198D1 DE 69319198 T DE69319198 T DE 69319198T DE 69319198 T DE69319198 T DE 69319198T DE 69319198 D1 DE69319198 D1 DE 69319198D1
Authority
DE
Germany
Prior art keywords
fuse
control circuit
improved control
circuit programmable
programmable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69319198T
Other languages
English (en)
Other versions
DE69319198T2 (de
Inventor
Yuichi Ashizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of DE69319198D1 publication Critical patent/DE69319198D1/de
Application granted granted Critical
Publication of DE69319198T2 publication Critical patent/DE69319198T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
DE69319198T 1992-10-08 1993-10-01 Durch Schmelzsicherung programmierbare verbesserte Steuerschaltung Expired - Lifetime DE69319198T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4270047A JP2991575B2 (ja) 1992-10-08 1992-10-08 半導体集積回路

Publications (2)

Publication Number Publication Date
DE69319198D1 true DE69319198D1 (de) 1998-07-23
DE69319198T2 DE69319198T2 (de) 1998-10-15

Family

ID=17480790

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69319198T Expired - Lifetime DE69319198T2 (de) 1992-10-08 1993-10-01 Durch Schmelzsicherung programmierbare verbesserte Steuerschaltung

Country Status (5)

Country Link
US (1) US5387823A (de)
EP (1) EP0591870B1 (de)
JP (1) JP2991575B2 (de)
KR (1) KR0163446B1 (de)
DE (1) DE69319198T2 (de)

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FR2718909B1 (fr) * 1994-04-18 1996-06-28 Transpac Matrice de connexion configurable électriquement entre lignes d'au moins un port d'entrée-sortie de signaux électriques.
US5528539A (en) * 1994-09-29 1996-06-18 Micron Semiconductor, Inc. High speed global row redundancy system
KR0145221B1 (ko) * 1995-05-25 1998-08-17 김광호 반도체 메모리 소자의 스위치 회로
US6198338B1 (en) * 1995-06-15 2001-03-06 Samsung Electronics Co., Ltd. Method of constructing a fuse for a semiconductor device and circuit using same
US6258609B1 (en) 1996-09-30 2001-07-10 Micron Technology, Inc. Method and system for making known good semiconductor dice
US6023431A (en) 1996-10-03 2000-02-08 Micron Technology, Inc. Low current redundancy anti-fuse method and apparatus
US5889414A (en) * 1997-04-28 1999-03-30 Mosel Vitelic Corporation Programmable circuits
JP3638757B2 (ja) * 1997-06-24 2005-04-13 株式会社 沖マイクロデザイン 半導体集積回路
US6014052A (en) * 1997-09-29 2000-01-11 Lsi Logic Corporation Implementation of serial fusible links
US9092595B2 (en) 1997-10-08 2015-07-28 Pact Xpp Technologies Ag Multiprocessor having associated RAM units
US6278468B1 (en) 1998-03-30 2001-08-21 Xerox Corporation Liquid ink printhead including a programmable temperature sensing device
US6037831A (en) * 1998-03-30 2000-03-14 Xerox Corporation Fusible link circuit including a preview feature
KR100301042B1 (ko) * 1998-07-15 2001-09-06 윤종용 레이아웃면적을최소화하는리던던시회로
TW446946B (en) * 1999-10-08 2001-07-21 Vanguard Int Semiconduct Corp Redundant decoder with fuse-controlled transistor
US6285619B1 (en) * 1999-11-18 2001-09-04 Infineon Technologies North America Corp. Memory cell
US6381115B1 (en) * 1999-12-20 2002-04-30 Stmicroelectronics, Inc. Redundant electric fuses
KR100389040B1 (ko) * 2000-10-18 2003-06-25 삼성전자주식회사 반도체 집적 회로의 퓨즈 회로
DE10056590A1 (de) 2000-11-15 2002-05-23 Philips Corp Intellectual Pty Schaltungsanordnung
JP3569225B2 (ja) * 2000-12-25 2004-09-22 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置
JP2003217294A (ja) 2001-11-16 2003-07-31 Fujitsu Ltd 半導体記憶装置、及び冗長判定方法
KR20030049667A (ko) * 2001-12-17 2003-06-25 삼성전자주식회사 퓨즈박스 내의 전류소모를 최소화한 반도체장치
US6704236B2 (en) 2002-01-03 2004-03-09 Broadcom Corporation Method and apparatus for verification of a gate oxide fuse element
JP4401194B2 (ja) * 2004-03-05 2010-01-20 Ｏｋｉセミコンダクタ株式会社 半導体装置
US7006393B2 (en) * 2004-06-07 2006-02-28 Micron Technology, Inc. Method and apparatus for semiconductor device repair with reduced number of programmable elements
US7218561B2 (en) * 2004-06-07 2007-05-15 Micron Technology, Inc. Apparatus and method for semiconductor device repair with reduced number of programmable elements
US7006394B2 (en) * 2004-06-07 2006-02-28 Micron Technology, Inc. Apparatus and method for semiconductor device repair with reduced number of programmable elements
JP4647294B2 (ja) * 2004-11-26 2011-03-09 ルネサスエレクトロニクス株式会社 半導体装置
US7548448B2 (en) 2005-08-24 2009-06-16 Infineon Technologies Ag Integrated circuit having a switch
KR100652428B1 (ko) * 2005-08-29 2006-12-01 삼성전자주식회사 반도체 메모리 장치의 리던던시 회로
JP2007273772A (ja) * 2006-03-31 2007-10-18 Fujitsu Ltd 半導体装置
JP5458236B2 (ja) * 2007-11-02 2014-04-02 ピーエスフォー ルクスコ エスエイアールエル 電気ヒューズ判定回路及び判定方法
US10153288B2 (en) * 2016-05-31 2018-12-11 Taiwan Semiconductor Manufacturing Company Limited Double metal layout for memory cells of a non-volatile memory

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228528B2 (en) * 1979-02-09 1992-10-06 Memory with redundant rows and columns
US4546455A (en) * 1981-12-17 1985-10-08 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device
JPS60101196U (ja) * 1983-12-13 1985-07-10 篠原　友義 筆記具
US4714983A (en) * 1985-06-10 1987-12-22 Motorola, Inc. Uniform emission backlight
JPS632351A (ja) * 1986-06-20 1988-01-07 Sharp Corp 半導体装置
US4689494A (en) * 1986-09-18 1987-08-25 Advanced Micro Devices, Inc. Redundancy enable/disable circuit
JPH02310898A (ja) * 1989-05-25 1990-12-26 Nec Corp メモリ回路
US4996670A (en) * 1989-09-28 1991-02-26 International Business Machines Corporation Zero standby power, radiation hardened, memory redundancy circuit
JPH03130999A (ja) * 1989-10-16 1991-06-04 Fujitsu Ltd 半導体集積回路
JP2679390B2 (ja) * 1990-10-12 1997-11-19 日本電気株式会社 コード設定回路
US5099149A (en) * 1990-12-19 1992-03-24 At&T Bell Laboratories Programmable integrated circuit
JP2689768B2 (ja) * 1991-07-08 1997-12-10 日本電気株式会社 半導体集積回路装置
US5262994A (en) * 1992-01-31 1993-11-16 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with a multiplexer for selecting an output for a redundant memory access
US5257229A (en) * 1992-01-31 1993-10-26 Sgs-Thomson Microelectronics, Inc. Column redundancy architecture for a read/write memory

Also Published As

Publication number Publication date
EP0591870B1 (de) 1998-06-17
KR0163446B1 (ko) 1999-02-01
JP2991575B2 (ja) 1999-12-20
US5387823A (en) 1995-02-07
JPH06124599A (ja) 1994-05-06
KR940010274A (ko) 1994-05-24
EP0591870A3 (de) 1995-01-18
EP0591870A2 (de) 1994-04-13
DE69319198T2 (de) 1998-10-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: PUSCHMANN & BORCHERT, 82041 OBERHACHING

8327 Change in the person/name/address of the patent owner

Owner name: OKI SEMICONDUCTOR CO.,LTD., TOKYO, JP