DE69318640D1 - Halbleitervorrichtung mit einem halbleitersubstrat und einer keramischen scheibe als decke - Google Patents

Halbleitervorrichtung mit einem halbleitersubstrat und einer keramischen scheibe als decke

Info

Publication number
DE69318640D1
DE69318640D1 DE69318640T DE69318640T DE69318640D1 DE 69318640 D1 DE69318640 D1 DE 69318640D1 DE 69318640 T DE69318640 T DE 69318640T DE 69318640 T DE69318640 T DE 69318640T DE 69318640 D1 DE69318640 D1 DE 69318640D1
Authority
DE
Germany
Prior art keywords
substrate
ceramic plate
ceiling
semiconductor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69318640T
Other languages
English (en)
Other versions
DE69318640T2 (de
Inventor
Victor Temple
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Harris Corp
Original Assignee
Harris Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Harris Corp filed Critical Harris Corp
Application granted granted Critical
Publication of DE69318640D1 publication Critical patent/DE69318640D1/de
Publication of DE69318640T2 publication Critical patent/DE69318640T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/049—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being perpendicular to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Die Bonding (AREA)
DE69318640T 1992-01-27 1993-01-19 Halbleitervorrichtung mit einem halbleitersubstrat und einer keramischen scheibe als decke Expired - Fee Related DE69318640T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US82600392A 1992-01-27 1992-01-27
PCT/US1993/000316 WO1993017456A1 (en) 1992-01-27 1993-01-19 Semiconductor devices and methods of mass production thereof

Publications (2)

Publication Number Publication Date
DE69318640D1 true DE69318640D1 (de) 1998-06-25
DE69318640T2 DE69318640T2 (de) 1998-09-10

Family

ID=25245440

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69318640T Expired - Fee Related DE69318640T2 (de) 1992-01-27 1993-01-19 Halbleitervorrichtung mit einem halbleitersubstrat und einer keramischen scheibe als decke

Country Status (7)

Country Link
US (2) US5521436A (de)
EP (1) EP0582694B1 (de)
JP (1) JPH10501656A (de)
AT (1) ATE166493T1 (de)
CA (1) CA2106981A1 (de)
DE (1) DE69318640T2 (de)
WO (1) WO1993017456A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0171921B1 (ko) * 1993-09-13 1999-03-30 모리시타 요이찌 전자부품과 그 제조방법
US5674343A (en) * 1994-04-19 1997-10-07 Nitto Denko Corporation Method for manufacturing a semiconductor
US5965933A (en) * 1996-05-28 1999-10-12 Young; William R. Semiconductor packaging apparatus
JPH10229059A (ja) * 1997-02-17 1998-08-25 Mitsubishi Electric Corp 半導体装置の製造方法および半導体装置
US6157076A (en) * 1997-06-30 2000-12-05 Intersil Corporation Hermetic thin pack semiconductor device
US7692211B1 (en) * 2001-07-03 2010-04-06 Silicon Power Corporation Super GTO-based power blocks
US9818903B2 (en) 2014-04-30 2017-11-14 Sunpower Corporation Bonds for solar cell metallization
CN107249287A (zh) * 2017-07-27 2017-10-13 维沃移动通信有限公司 一种电子组件及电子设备

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE584431A (de) * 1959-02-09
NL270369A (de) * 1961-01-16
US4249034A (en) * 1978-11-27 1981-02-03 General Electric Company Semiconductor package having strengthening and sealing upper chamber
US4646129A (en) * 1983-09-06 1987-02-24 General Electric Company Hermetic power chip packages
JPS60115247A (ja) * 1983-11-28 1985-06-21 Fujitsu Ltd 半導体装置
US4769272A (en) * 1987-03-17 1988-09-06 National Semiconductor Corporation Ceramic lid hermetic seal package structure
JPH02306639A (ja) * 1989-05-22 1990-12-20 Toshiba Corp 半導体装置の樹脂封入方法
US5135890A (en) * 1989-06-16 1992-08-04 General Electric Company Method of forming a hermetic package having a lead extending through an aperture in the package lid and packaged semiconductor chip
US5028987A (en) * 1989-07-03 1991-07-02 General Electric Company High current hermetic package having a lead extending through the package lid and a packaged semiconductor chip
US5166773A (en) * 1989-07-03 1992-11-24 General Electric Company Hermetic package and packaged semiconductor chip having closely spaced leads extending through the package lid
US5073521A (en) * 1989-11-15 1991-12-17 Olin Corporation Method for housing a tape-bonded electronic device and the package employed
US5164328A (en) * 1990-06-25 1992-11-17 Motorola, Inc. Method of bump bonding and sealing an accelerometer chip onto an integrated circuit chip
US5155067A (en) * 1991-03-26 1992-10-13 Micron Technology, Inc. Packaging for a semiconductor die
US5248901A (en) * 1992-01-21 1993-09-28 Harris Corporation Semiconductor devices and methods of assembly thereof
US5405808A (en) * 1993-08-16 1995-04-11 Lsi Logic Corporation Fluid-filled and gas-filled semiconductor packages

Also Published As

Publication number Publication date
ATE166493T1 (de) 1998-06-15
WO1993017456A1 (en) 1993-09-02
CA2106981A1 (en) 1993-07-28
DE69318640T2 (de) 1998-09-10
US5521436A (en) 1996-05-28
EP0582694A1 (de) 1994-02-16
EP0582694B1 (de) 1998-05-20
US5585310A (en) 1996-12-17
JPH10501656A (ja) 1998-02-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee