JPS553610A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS553610A JPS553610A JP7419278A JP7419278A JPS553610A JP S553610 A JPS553610 A JP S553610A JP 7419278 A JP7419278 A JP 7419278A JP 7419278 A JP7419278 A JP 7419278A JP S553610 A JPS553610 A JP S553610A
- Authority
- JP
- Japan
- Prior art keywords
- package
- leads
- base
- ceramic
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
PURPOSE: To requlate the mounting position of leads, installed at the four corners on a ceramic package, in the level direction of the package by providing the leads with projections which engage the bottom surface of package.
CONSTITUTION: The ceramic package 10 is composed of a ceramic base 12, a ceramic frame 13 stacked on the base 12, and a cap 14 put on the frame 13. In this case, a large number of metalized layers 18 extending from the side to the bottom surfaces through the underneath of the frame 13 are disposed on the upper surface of base 12, and a semiconductor IC chip 22 is secured to a recess at the center of base 12 through the metalized layer 20. In the next step, respective electrodes on the chip 22 are coupled to the metalized layer 18 by use of bonding wires 26 and secured in a line at the side of package to the corresponding leads. In this constitution, the leads 16AW16D are provided with positioning projections 16b which, through punched holes 16a, can engage the bottom surface of package, thus accuring that the leads can be aligned in the level direction.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7419278A JPS553610A (en) | 1978-06-21 | 1978-06-21 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7419278A JPS553610A (en) | 1978-06-21 | 1978-06-21 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS553610A true JPS553610A (en) | 1980-01-11 |
Family
ID=13540057
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7419278A Pending JPS553610A (en) | 1978-06-21 | 1978-06-21 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS553610A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5810478U (en) * | 1981-07-09 | 1983-01-22 | 日本電気株式会社 | display panel |
-
1978
- 1978-06-21 JP JP7419278A patent/JPS553610A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5810478U (en) * | 1981-07-09 | 1983-01-22 | 日本電気株式会社 | display panel |
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