DE69314584T2 - Verfahren und Muster zur Rauschverminderung in integrierten Schaltungsanordnungen - Google Patents

Verfahren und Muster zur Rauschverminderung in integrierten Schaltungsanordnungen

Info

Publication number
DE69314584T2
DE69314584T2 DE69314584T DE69314584T DE69314584T2 DE 69314584 T2 DE69314584 T2 DE 69314584T2 DE 69314584 T DE69314584 T DE 69314584T DE 69314584 T DE69314584 T DE 69314584T DE 69314584 T2 DE69314584 T2 DE 69314584T2
Authority
DE
Germany
Prior art keywords
bit lines
chip
lead frame
dielectric constant
boundary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69314584T
Other languages
German (de)
English (en)
Other versions
DE69314584D1 (de
Inventor
Michael A Van Lamson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69314584D1 publication Critical patent/DE69314584D1/de
Application granted granted Critical
Publication of DE69314584T2 publication Critical patent/DE69314584T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H10W70/415—Leadframe inner leads serving as die pads
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
DE69314584T 1992-09-02 1993-08-23 Verfahren und Muster zur Rauschverminderung in integrierten Schaltungsanordnungen Expired - Fee Related DE69314584T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US93918892A 1992-09-02 1992-09-02

Publications (2)

Publication Number Publication Date
DE69314584D1 DE69314584D1 (de) 1997-11-20
DE69314584T2 true DE69314584T2 (de) 1998-02-19

Family

ID=25472701

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69314584T Expired - Fee Related DE69314584T2 (de) 1992-09-02 1993-08-23 Verfahren und Muster zur Rauschverminderung in integrierten Schaltungsanordnungen

Country Status (6)

Country Link
US (1) US5334802A (enExample)
EP (1) EP0586163B1 (enExample)
JP (1) JPH0794660A (enExample)
KR (1) KR100281986B1 (enExample)
DE (1) DE69314584T2 (enExample)
TW (1) TW229331B (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6525976B1 (en) 2000-10-24 2003-02-25 Excellatron Solid State, Llc Systems and methods for reducing noise in mixed-mode integrated circuits
KR20030084086A (ko) * 2002-04-24 2003-11-01 엑셀라트론 솔리드 스테이트 엘엘씨 혼합-모드 집적회로의 노이즈 감소를 위한 시스템 및 방법
US7830221B2 (en) * 2008-01-25 2010-11-09 Micron Technology, Inc. Coupling cancellation scheme

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862245A (en) * 1985-04-18 1989-08-29 International Business Machines Corporation Package semiconductor chip
US5068712A (en) * 1988-09-20 1991-11-26 Hitachi, Ltd. Semiconductor device
JPH0279463A (ja) * 1988-09-14 1990-03-20 Mitsubishi Electric Corp 半導体記憶装置
US4916519A (en) * 1989-05-30 1990-04-10 International Business Machines Corporation Semiconductor package
SG49886A1 (en) * 1989-06-30 1998-06-15 Texas Instruments Inc Balanced capacitance lead frame for integrated circuits
JPH088330B2 (ja) * 1989-07-19 1996-01-29 日本電気株式会社 Ｌｏｃ型リードフレームを備えた半導体集積回路装置
US4965654A (en) * 1989-10-30 1990-10-23 International Business Machines Corporation Semiconductor package with ground plane
US5197184A (en) * 1990-09-11 1993-03-30 Hughes Aircraft Company Method of forming three-dimensional circuitry

Also Published As

Publication number Publication date
DE69314584D1 (de) 1997-11-20
EP0586163B1 (en) 1997-10-15
EP0586163A3 (enExample) 1994-03-23
KR940008023A (ko) 1994-04-28
JPH0794660A (ja) 1995-04-07
US5334802A (en) 1994-08-02
EP0586163A2 (en) 1994-03-09
TW229331B (enExample) 1994-09-01
KR100281986B1 (ko) 2001-03-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee