DE69314584T2 - Verfahren und Muster zur Rauschverminderung in integrierten Schaltungsanordnungen - Google Patents

Verfahren und Muster zur Rauschverminderung in integrierten Schaltungsanordnungen

Info

Publication number
DE69314584T2
DE69314584T2 DE69314584T DE69314584T DE69314584T2 DE 69314584 T2 DE69314584 T2 DE 69314584T2 DE 69314584 T DE69314584 T DE 69314584T DE 69314584 T DE69314584 T DE 69314584T DE 69314584 T2 DE69314584 T2 DE 69314584T2
Authority
DE
Germany
Prior art keywords
patterns
methods
integrated circuit
noise reduction
circuit arrangements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69314584T
Other languages
English (en)
Other versions
DE69314584D1 (de
Inventor
Michael A Van Lamson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69314584D1 publication Critical patent/DE69314584D1/de
Publication of DE69314584T2 publication Critical patent/DE69314584T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
DE69314584T 1992-09-02 1993-08-23 Verfahren und Muster zur Rauschverminderung in integrierten Schaltungsanordnungen Expired - Fee Related DE69314584T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US93918892A 1992-09-02 1992-09-02

Publications (2)

Publication Number Publication Date
DE69314584D1 DE69314584D1 (de) 1997-11-20
DE69314584T2 true DE69314584T2 (de) 1998-02-19

Family

ID=25472701

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69314584T Expired - Fee Related DE69314584T2 (de) 1992-09-02 1993-08-23 Verfahren und Muster zur Rauschverminderung in integrierten Schaltungsanordnungen

Country Status (6)

Country Link
US (1) US5334802A (de)
EP (1) EP0586163B1 (de)
JP (1) JPH0794660A (de)
KR (1) KR100281986B1 (de)
DE (1) DE69314584T2 (de)
TW (1) TW229331B (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6525976B1 (en) 2000-10-24 2003-02-25 Excellatron Solid State, Llc Systems and methods for reducing noise in mixed-mode integrated circuits
KR20030084086A (ko) * 2002-04-24 2003-11-01 엑셀라트론 솔리드 스테이트 엘엘씨 혼합-모드 집적회로의 노이즈 감소를 위한 시스템 및 방법
US7830221B2 (en) * 2008-01-25 2010-11-09 Micron Technology, Inc. Coupling cancellation scheme

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862245A (en) * 1985-04-18 1989-08-29 International Business Machines Corporation Package semiconductor chip
JPH0279463A (ja) * 1988-09-14 1990-03-20 Mitsubishi Electric Corp 半導体記憶装置
KR0158868B1 (ko) * 1988-09-20 1998-12-01 미다 가쓰시게 반도체장치
US4916519A (en) * 1989-05-30 1990-04-10 International Business Machines Corporation Semiconductor package
EP0405871B1 (de) * 1989-06-30 1999-09-08 Texas Instruments Incorporated Anschlussrahmen mit ausgeglichener Kapazität für integrierte Schaltungen
JPH088330B2 (ja) * 1989-07-19 1996-01-29 日本電気株式会社 Ｌｏｃ型リードフレームを備えた半導体集積回路装置
US4965654A (en) * 1989-10-30 1990-10-23 International Business Machines Corporation Semiconductor package with ground plane
US5197184A (en) * 1990-09-11 1993-03-30 Hughes Aircraft Company Method of forming three-dimensional circuitry

Also Published As

Publication number Publication date
EP0586163A2 (de) 1994-03-09
DE69314584D1 (de) 1997-11-20
JPH0794660A (ja) 1995-04-07
KR940008023A (ko) 1994-04-28
US5334802A (en) 1994-08-02
KR100281986B1 (ko) 2001-03-02
EP0586163A3 (de) 1994-03-23
TW229331B (de) 1994-09-01
EP0586163B1 (de) 1997-10-15

Similar Documents

Publication Publication Date Title
DE69329670D1 (de) Verfahren und Gerät zur Rauschminderung
DE69328602D1 (de) Schaltungen zur Rauschunterdrückung
DE69324637D1 (de) Sicherheitssystem für integrierte Schaltung und Verfahren mit implantierten Leitungen
DE69534700D1 (de) Halbleiteranordnungen und verfahren
DE69531710D1 (de) Verfahren und Vorrichtung zur Verminderung von Rauschen bei Sprachsignalen
DE69430838T2 (de) Schaltung und Verfahren zur parallelen Verschiebung und Addition
DE69323015T2 (de) Verfahren und Anordnung zur Reprogrammierung
DE69621517D1 (de) Integrierte monolithische Mikrowellenschaltung und Verfahren
DE69435047D1 (de) Schaltung und Verfahren zur parallelen Addition und Mittelwertbildung
DE19882396T1 (de) Verfahren zur Verbesserung elektromagnetischer Strahlungseigenschaften verkapselter Schaltungen und damit in Beziehung stehende Vorrichtungen
DE69731700D1 (de) Arithmetischer Schaltkreis und arithmetisches Verfahren
DE69706043D1 (de) Integrierte schaltungsschutzanordnung und verfahren
DE69324100D1 (de) Schaltung und Verfahren für Rauschformung
DE69126651D1 (de) Verfahren und Vorrichtungen zur Reduzierung von Koppelungsstörungen in programmierbaren logischen Anordnungen
DE69322233D1 (de) Elektronisches Teil mit metallischen Leiterbahnen und Verfahren zu seiner Herstellung
DE69717216T2 (de) Schaltplatinenprüfvorrichtung und Verfahren dafür
DE69417297T2 (de) Schaltung und Verfahren zur Unterdrückung von Störsignalen
DE69218359T2 (de) Verfahren und Schaltung für Rauschformung
DE69627948D1 (de) Rechenschaltung mit sofortiger Erkennungsfunktion und Verfahren zur sofortigen Erkennung
DE69111402T2 (de) Verfahren und Gerät zur Lärmdämpfung.
DE69314584T2 (de) Verfahren und Muster zur Rauschverminderung in integrierten Schaltungsanordnungen
DE69532061D1 (de) Verstärkerschaltung und Verfahren
DE69229571T2 (de) Anordnung und Verfahren zur Informationseinfügung und Ausblendung in Übertragungsleitungen
DE69423073D1 (de) Schaltung und Verfahren zur Verschiebung und Abrundung
DE69617082D1 (de) Schaltung und Verfahren zur Behandlung fälschlicher Nulldurchgänge in Signalen geringer Intensität

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee