DE69435047D1 - Schaltung und Verfahren zur parallelen Addition und Mittelwertbildung - Google Patents

Schaltung und Verfahren zur parallelen Addition und Mittelwertbildung

Info

Publication number
DE69435047D1
DE69435047D1 DE69435047T DE69435047T DE69435047D1 DE 69435047 D1 DE69435047 D1 DE 69435047D1 DE 69435047 T DE69435047 T DE 69435047T DE 69435047 T DE69435047 T DE 69435047T DE 69435047 D1 DE69435047 D1 DE 69435047D1
Authority
DE
Germany
Prior art keywords
averaging
circuit
parallel addition
parallel
addition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69435047T
Other languages
English (en)
Other versions
DE69435047T2 (de
Inventor
Ruby Bei-Loh Lee
John Paul Beck
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE69435047D1 publication Critical patent/DE69435047D1/de
Publication of DE69435047T2 publication Critical patent/DE69435047T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/382—Reconfigurable for different fixed word lengths
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49963—Rounding to nearest
DE69435047T 1993-11-29 1994-08-02 Schaltung und Verfahren zur parallelen Addition und Mittelwertbildung Expired - Fee Related DE69435047T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/158,649 US5883824A (en) 1993-11-29 1993-11-29 Parallel adding and averaging circuit and method
US158649 1993-11-29

Publications (2)

Publication Number Publication Date
DE69435047D1 true DE69435047D1 (de) 2008-01-03
DE69435047T2 DE69435047T2 (de) 2008-10-02

Family

ID=22569081

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69435047T Expired - Fee Related DE69435047T2 (de) 1993-11-29 1994-08-02 Schaltung und Verfahren zur parallelen Addition und Mittelwertbildung

Country Status (4)

Country Link
US (1) US5883824A (de)
EP (1) EP0656582B1 (de)
JP (1) JP3729881B2 (de)
DE (1) DE69435047T2 (de)

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US5742840A (en) * 1995-08-16 1998-04-21 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor
US6643765B1 (en) * 1995-08-16 2003-11-04 Microunity Systems Engineering, Inc. Programmable processor with group floating point operations
US6295599B1 (en) * 1995-08-16 2001-09-25 Microunity Systems Engineering System and method for providing a wide operand architecture
US7301541B2 (en) * 1995-08-16 2007-11-27 Microunity Systems Engineering, Inc. Programmable processor and method with wide operations
US5953241A (en) * 1995-08-16 1999-09-14 Microunity Engeering Systems, Inc. Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction
US7395298B2 (en) * 1995-08-31 2008-07-01 Intel Corporation Method and apparatus for performing multiply-add operations on packed data
US6385634B1 (en) * 1995-08-31 2002-05-07 Intel Corporation Method for performing multiply-add operations on packed data
WO1997009679A1 (en) * 1995-09-01 1997-03-13 Philips Electronics North America Corporation Method and apparatus for custom processor operations
US6003125A (en) * 1997-01-24 1999-12-14 Texas Instruments Incorporated High performance adder for multiple parallel add operations
US6408320B1 (en) * 1998-01-27 2002-06-18 Texas Instruments Incorporated Instruction set architecture with versatile adder carry control
US6418529B1 (en) * 1998-03-31 2002-07-09 Intel Corporation Apparatus and method for performing intra-add operation
US7395302B2 (en) 1998-03-31 2008-07-01 Intel Corporation Method and apparatus for performing horizontal addition and subtraction
US7392275B2 (en) * 1998-03-31 2008-06-24 Intel Corporation Method and apparatus for performing efficient transformations with horizontal addition and subtraction
US6230253B1 (en) * 1998-03-31 2001-05-08 Intel Corporation Executing partial-width packed data instructions
US6230257B1 (en) * 1998-03-31 2001-05-08 Intel Corporation Method and apparatus for staggering execution of a single packed data instruction using the same circuit
US6211892B1 (en) * 1998-03-31 2001-04-03 Intel Corporation System and method for performing an intra-add operation
US6449629B1 (en) * 1999-05-12 2002-09-10 Agere Systems Guardian Corp. Three input split-adder
US6512523B1 (en) * 2000-03-27 2003-01-28 Intel Corporation Accurate averaging of elements using integer averaging
GB2362732B (en) * 2000-05-23 2004-08-04 Advanced Risc Mach Ltd Parallel processing of multiple data values within a data word
US6748411B1 (en) * 2000-11-20 2004-06-08 Agere Systems Inc. Hierarchical carry-select multiple-input split adder
US7430578B2 (en) * 2001-10-29 2008-09-30 Intel Corporation Method and apparatus for performing multiply-add operations on packed byte data
US7219118B2 (en) * 2001-11-06 2007-05-15 Broadcom Corporation SIMD addition circuit
US7558816B2 (en) * 2001-11-21 2009-07-07 Sun Microsystems, Inc. Methods and apparatus for performing pixel average operations
US7254599B2 (en) * 2002-05-30 2007-08-07 Sun Microsystems, Inc. Average code generation circuit
US7149768B2 (en) * 2002-10-15 2006-12-12 Ceva D.S.P. Ltd. 3-input arithmetic logic unit
JP4317738B2 (ja) * 2003-12-17 2009-08-19 富士通株式会社 平均値算出装置および平均値算出方法
US20090070400A1 (en) * 2007-09-12 2009-03-12 Technology Properties Limited Carry-select adder
US8036484B2 (en) * 2007-10-16 2011-10-11 Broadcom Corporation In-place averaging of packed pixel data
EP2181504A4 (de) * 2008-08-15 2010-07-28 Lsi Corp Rom-listen-decodierung von nah-codewörtern
US9524572B2 (en) * 2010-11-23 2016-12-20 Microsoft Technology Licensing, Llc Parallel processing of pixel data
KR102072543B1 (ko) * 2013-01-28 2020-02-03 삼성전자 주식회사 복수 데이터 형식을 지원하는 가산기 및 그 가산기를 이용한 복수 데이터 형식의 가감 연산 지원 방법

Family Cites Families (10)

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Publication number Priority date Publication date Assignee Title
US3987291A (en) * 1975-05-01 1976-10-19 International Business Machines Corporation Parallel digital arithmetic device having a variable number of independent arithmetic zones of variable width and location
US4137568A (en) * 1977-04-11 1979-01-30 Pitney-Bowes, Inc. Circuit for establishing the average value of a number of input values
JPS59161731A (ja) * 1983-03-07 1984-09-12 Hitachi Ltd バレルシフタ
JPS6124331A (ja) * 1984-07-12 1986-02-03 Nec Corp アナログ−デイジタル変換器
US4707800A (en) * 1985-03-04 1987-11-17 Raytheon Company Adder/substractor for variable length numbers
DE3509762A1 (de) * 1985-03-19 1986-09-25 Battelle-Institut E.V., 6000 Frankfurt Schaltungsanordnung zur mittelwertbildung
JPS61239327A (ja) * 1985-04-16 1986-10-24 Nec Corp オ−バフロ−検出方式
US4914617A (en) * 1987-06-26 1990-04-03 International Business Machines Corporation High performance parallel binary byte adder
US5189636A (en) * 1987-11-16 1993-02-23 Intel Corporation Dual mode combining circuitry
US5047975A (en) * 1987-11-16 1991-09-10 Intel Corporation Dual mode adder circuitry with overflow detection and substitution enabled for a particular mode

Also Published As

Publication number Publication date
EP0656582B1 (de) 2007-11-21
US5883824A (en) 1999-03-16
DE69435047T2 (de) 2008-10-02
JPH07210369A (ja) 1995-08-11
JP3729881B2 (ja) 2005-12-21
EP0656582A1 (de) 1995-06-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee