DE69231236D1 - Integrierte Halbleiterschaltungsanordnung mit auf unterschiedliche Spannungen vorgespannten Wannen - Google Patents

Integrierte Halbleiterschaltungsanordnung mit auf unterschiedliche Spannungen vorgespannten Wannen

Info

Publication number
DE69231236D1
DE69231236D1 DE69231236T DE69231236T DE69231236D1 DE 69231236 D1 DE69231236 D1 DE 69231236D1 DE 69231236 T DE69231236 T DE 69231236T DE 69231236 T DE69231236 T DE 69231236T DE 69231236 D1 DE69231236 D1 DE 69231236D1
Authority
DE
Germany
Prior art keywords
circuit arrangement
semiconductor circuit
different voltages
integrated semiconductor
wells biased
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69231236T
Other languages
English (en)
Other versions
DE69231236T2 (de
Inventor
Yasutaka Nakashiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69231236D1 publication Critical patent/DE69231236D1/de
Application granted granted Critical
Publication of DE69231236T2 publication Critical patent/DE69231236T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69231236T 1991-05-02 1992-04-22 Integrierte Halbleiterschaltungsanordnung mit auf unterschiedliche Spannungen vorgespannten Wannen Expired - Fee Related DE69231236T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3130547A JP2757583B2 (ja) 1991-05-02 1991-05-02 半導体集積回路

Publications (2)

Publication Number Publication Date
DE69231236D1 true DE69231236D1 (de) 2000-08-17
DE69231236T2 DE69231236T2 (de) 2001-02-22

Family

ID=15036891

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69231236T Expired - Fee Related DE69231236T2 (de) 1991-05-02 1992-04-22 Integrierte Halbleiterschaltungsanordnung mit auf unterschiedliche Spannungen vorgespannten Wannen

Country Status (4)

Country Link
US (1) US5289029A (de)
EP (1) EP0515833B1 (de)
JP (1) JP2757583B2 (de)
DE (1) DE69231236T2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3297988B2 (ja) * 1997-01-24 2002-07-02 シャープ株式会社 アクティブマトリクス基板
US6943614B1 (en) * 2004-01-29 2005-09-13 Transmeta Corporation Fractional biasing of semiconductors

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1131675A (en) * 1966-07-11 1968-10-23 Hitachi Ltd Semiconductor device
US4458262A (en) * 1980-05-27 1984-07-03 Supertex, Inc. CMOS Device with ion-implanted channel-stop region and fabrication method therefor
DE3579391D1 (de) * 1984-02-21 1990-10-04 American Telephone & Telegraph Generisches mehrzweckchipsubstrat.
JPS6155962A (ja) * 1984-08-27 1986-03-20 Oki Electric Ind Co Ltd 電荷結合素子
JPH02220451A (ja) * 1989-02-22 1990-09-03 Fuji Photo Film Co Ltd Ｃｃｄ遅延線
JPH02226743A (ja) * 1989-02-28 1990-09-10 Mitsubishi Electric Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
EP0515833A1 (de) 1992-12-02
US5289029A (en) 1994-02-22
JP2757583B2 (ja) 1998-05-25
EP0515833B1 (de) 2000-07-12
JPH04332167A (ja) 1992-11-19
DE69231236T2 (de) 2001-02-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee