DE69226328T2 - Selbstjustierende Kontaktstützer für Halbleitervorrichtungen - Google Patents

Selbstjustierende Kontaktstützer für Halbleitervorrichtungen

Info

Publication number
DE69226328T2
DE69226328T2 DE69226328T DE69226328T DE69226328T2 DE 69226328 T2 DE69226328 T2 DE 69226328T2 DE 69226328 T DE69226328 T DE 69226328T DE 69226328 T DE69226328 T DE 69226328T DE 69226328 T2 DE69226328 T2 DE 69226328T2
Authority
DE
Germany
Prior art keywords
spacer
gate conductor
alignment structure
layer
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69226328T
Other languages
German (de)
English (en)
Other versions
DE69226328D1 (de
Inventor
Donna Rizzone Pourhquag New York 12570 Cote
David Wappingers Falls New York 12590 Stanasolovich
Ronald Archer Essex Junction Vermont 05452 Warren
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69226328D1 publication Critical patent/DE69226328D1/de
Publication of DE69226328T2 publication Critical patent/DE69226328T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H10W20/42—
    • H10P95/00—
    • H10W20/056—
    • H10W20/057—
    • H10W20/069—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE69226328T 1991-10-29 1992-10-09 Selbstjustierende Kontaktstützer für Halbleitervorrichtungen Expired - Fee Related DE69226328T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/784,193 US5216282A (en) 1991-10-29 1991-10-29 Self-aligned contact studs for semiconductor structures

Publications (2)

Publication Number Publication Date
DE69226328D1 DE69226328D1 (de) 1998-08-27
DE69226328T2 true DE69226328T2 (de) 1999-03-25

Family

ID=25131638

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69226328T Expired - Fee Related DE69226328T2 (de) 1991-10-29 1992-10-09 Selbstjustierende Kontaktstützer für Halbleitervorrichtungen

Country Status (4)

Country Link
US (2) US5216282A (enExample)
EP (1) EP0540446B1 (enExample)
JP (1) JP2505961B2 (enExample)
DE (1) DE69226328T2 (enExample)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970009274B1 (ko) * 1991-11-11 1997-06-09 미쓰비시덴키 가부시키가이샤 반도체장치의 도전층접속구조 및 그 제조방법
US5364817A (en) * 1994-05-05 1994-11-15 United Microelectronics Corporation Tungsten-plug process
JP3256084B2 (ja) * 1994-05-26 2002-02-12 株式会社半導体エネルギー研究所 半導体集積回路およびその作製方法
US5380671A (en) * 1994-06-13 1995-01-10 United Microelectronics Corporation Method of making non-trenched buried contact for VLSI devices
US5512514A (en) * 1994-11-08 1996-04-30 Spider Systems, Inc. Self-aligned via and contact interconnect manufacturing method
US5879955A (en) * 1995-06-07 1999-03-09 Micron Technology, Inc. Method for fabricating an array of ultra-small pores for chalcogenide memory cells
US5684331A (en) * 1995-06-07 1997-11-04 Lg Semicon Co., Ltd. Multilayered interconnection of semiconductor device
US6420725B1 (en) * 1995-06-07 2002-07-16 Micron Technology, Inc. Method and apparatus for forming an integrated circuit electrode having a reduced contact area
US5714039A (en) * 1995-10-04 1998-02-03 International Business Machines Corporation Method for making sub-lithographic images by etching the intersection of two spacers
US5960318A (en) * 1995-10-27 1999-09-28 Siemens Aktiengesellschaft Borderless contact etch process with sidewall spacer and selective isotropic etch process
US6653733B1 (en) 1996-02-23 2003-11-25 Micron Technology, Inc. Conductors in semiconductor devices
US6337266B1 (en) 1996-07-22 2002-01-08 Micron Technology, Inc. Small electrode for chalcogenide memories
US6015977A (en) 1997-01-28 2000-01-18 Micron Technology, Inc. Integrated circuit memory cell having a small active area and method of forming same
US6724088B1 (en) 1999-04-20 2004-04-20 International Business Machines Corporation Quantum conductive barrier for contact to shallow diffusion region
US6399434B1 (en) 2000-04-26 2002-06-04 International Business Machines Corporation Doped structures containing diffusion barriers
US6563156B2 (en) 2001-03-15 2003-05-13 Micron Technology, Inc. Memory elements and methods for making same
US7084423B2 (en) 2002-08-12 2006-08-01 Acorn Technologies, Inc. Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US6833556B2 (en) 2002-08-12 2004-12-21 Acorn Technologies, Inc. Insulated gate field effect transistor having passivated schottky barriers to the channel
US20040036171A1 (en) * 2002-08-22 2004-02-26 Farnworth Warren M. Method and apparatus for enabling a stitch wire bond in the absence of discrete bump formation, semiconductor device assemblies and electronic systems including same
KR100485690B1 (ko) * 2002-10-26 2005-04-27 삼성전자주식회사 모스 트랜지스터 및 그 제조방법
JP5134326B2 (ja) * 2007-09-25 2013-01-30 株式会社渡辺商行 半導体装置の製造方法
GB2526951B (en) 2011-11-23 2016-04-20 Acorn Tech Inc Improving metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
JP2012094900A (ja) * 2012-01-26 2012-05-17 Watanabe Shoko:Kk Ｂｃｎ系の絶縁膜及びその製造方法並びに半導体装置
US9620611B1 (en) 2016-06-17 2017-04-11 Acorn Technology, Inc. MIS contact structure with metal oxide conductor
DE112017005855T5 (de) 2016-11-18 2019-08-01 Acorn Technologies, Inc. Nanodrahttransistor mit Source und Drain induziert durch elektrische Kontakte mit negativer Schottky-Barrierenhöhe

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4476482A (en) * 1981-05-29 1984-10-09 Texas Instruments Incorporated Silicide contacts for CMOS devices
EP0075454B1 (en) * 1981-09-18 1987-11-25 Fujitsu Limited Semiconductor device having new conductive interconnection structure and method for manufacturing the same
CA1298921C (en) * 1986-07-02 1992-04-14 Madhukar B. Vora Bipolar transistor with polysilicon stringer base contact
US4980752A (en) * 1986-12-29 1990-12-25 Inmos Corporation Transition metal clad interconnect for integrated circuits
US4939154A (en) * 1987-03-25 1990-07-03 Seiko Instruments Inc. Method of fabricating an insulated gate semiconductor device having a self-aligned gate
JPS63278256A (ja) * 1987-05-09 1988-11-15 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH0622235B2 (ja) * 1987-05-21 1994-03-23 日本電気株式会社 半導体装置の製造方法
US4837609A (en) * 1987-09-09 1989-06-06 American Telephone And Telegraph Company, At&T Bell Laboratories Semiconductor devices having superconducting interconnects
US5057902A (en) * 1987-12-02 1991-10-15 Advanced Micro Devices, Inc. Self-aligned semiconductor devices
JPH01214067A (ja) * 1988-02-22 1989-08-28 Nec Corp ゲート電極及び配線とその製造方法
JPH01214168A (ja) * 1988-02-23 1989-08-28 Nec Corp 半導体装置及びその製造方法
JPH0666329B2 (ja) * 1988-06-30 1994-08-24 株式会社東芝 半導体装置の製造方法
US5136533A (en) * 1988-07-08 1992-08-04 Eliyahou Harari Sidewall capacitor DRAM cell
JPH0284741A (ja) * 1988-09-21 1990-03-26 Nec Corp 半導体装置の製造方法
EP0363297B1 (en) * 1988-10-03 1994-03-23 International Business Machines Corporation Improved contact stud structure for semiconductor devices
US5060029A (en) * 1989-02-28 1991-10-22 Small Power Communication Systems Research Laboratories Co., Ltd. Step cut type insulated gate SIT having low-resistance electrode and method of manufacturing the same
US4960723A (en) * 1989-03-30 1990-10-02 Motorola, Inc. Process for making a self aligned vertical field effect transistor having an improved source contact
US5043786A (en) * 1989-04-13 1991-08-27 International Business Machines Corporation Lateral transistor and method of making same
US5132755A (en) * 1989-07-11 1992-07-21 Oki Electric Industry Co. Ltd. Field effect transistor

Also Published As

Publication number Publication date
EP0540446A2 (en) 1993-05-05
JP2505961B2 (ja) 1996-06-12
EP0540446B1 (en) 1998-07-22
EP0540446A3 (enExample) 1994-03-16
DE69226328D1 (de) 1998-08-27
JPH05226478A (ja) 1993-09-03
US5352927A (en) 1994-10-04
US5216282A (en) 1993-06-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee