DE69221966D1 - Halbleiteranordnung mit verschmolzenen bipolaren und MOS-Transistoren und Herstellungsverfahren - Google Patents

Halbleiteranordnung mit verschmolzenen bipolaren und MOS-Transistoren und Herstellungsverfahren

Info

Publication number
DE69221966D1
DE69221966D1 DE69221966T DE69221966T DE69221966D1 DE 69221966 D1 DE69221966 D1 DE 69221966D1 DE 69221966 T DE69221966 T DE 69221966T DE 69221966 T DE69221966 T DE 69221966T DE 69221966 D1 DE69221966 D1 DE 69221966D1
Authority
DE
Germany
Prior art keywords
bipolar
fused
semiconductor device
manufacturing process
mos transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69221966T
Other languages
English (en)
Other versions
DE69221966T2 (de
Inventor
James D Hayden
Thomas C Mele
Frank K Baker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE69221966D1 publication Critical patent/DE69221966D1/de
Publication of DE69221966T2 publication Critical patent/DE69221966T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
    • H01L27/0716—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/74—Array wherein each memory cell has more than one access device

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
DE69221966T 1991-07-01 1992-06-30 Halbleiteranordnung mit verschmolzenen bipolaren und MOS-Transistoren und Herstellungsverfahren Expired - Fee Related DE69221966T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/724,285 US5101257A (en) 1991-07-01 1991-07-01 Semiconductor device having merged bipolar and MOS transistors and process for making the same

Publications (2)

Publication Number Publication Date
DE69221966D1 true DE69221966D1 (de) 1997-10-09
DE69221966T2 DE69221966T2 (de) 1998-03-12

Family

ID=24909807

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69221966T Expired - Fee Related DE69221966T2 (de) 1991-07-01 1992-06-30 Halbleiteranordnung mit verschmolzenen bipolaren und MOS-Transistoren und Herstellungsverfahren

Country Status (5)

Country Link
US (1) US5101257A (de)
EP (1) EP0521702B1 (de)
JP (1) JPH05190780A (de)
KR (1) KR100227710B1 (de)
DE (1) DE69221966T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100200397B1 (ko) * 1990-07-23 1999-06-15 야스카와 히데아키 반도체장치 및 그 제조방법
US5387811A (en) * 1991-01-25 1995-02-07 Nec Corporation Composite semiconductor device with a particular bipolar structure
US5629547A (en) * 1991-04-23 1997-05-13 Intel Corporation BICMOS process for counter doped collector
GB2255226B (en) * 1991-04-23 1995-03-01 Intel Corp Bicmos process for counter doped collector
US5416031A (en) * 1992-09-30 1995-05-16 Sony Corporation Method of producing Bi-CMOS transistors
KR960012252B1 (ko) * 1993-03-05 1996-09-18 삼성전자 주식회사 반도체 메모리장치
US5438009A (en) * 1993-04-02 1995-08-01 United Microelectronics Corporation Method of fabrication of MOSFET device with buried bit line
DE69434183D1 (de) * 1993-10-22 2005-01-20 Zetex Plc MOS/bipolar Anordnung
GB9321819D0 (en) * 1993-10-22 1993-12-15 Zetex Plc Mos/bipolar device
US5441903A (en) * 1993-12-03 1995-08-15 Texas Instruments Incorporated BiCMOS process for supporting merged devices
US5538908A (en) * 1995-04-27 1996-07-23 Lg Semicon Co., Ltd. Method for manufacturing a BiCMOS semiconductor device
US5684313A (en) * 1996-02-20 1997-11-04 Kenney; Donald M. Vertical precharge structure for DRAM
US5741737A (en) * 1996-06-27 1998-04-21 Cypress Semiconductor Corporation MOS transistor with ramped gate oxide thickness and method for making same
JP3244065B2 (ja) * 1998-10-23 2002-01-07 日本電気株式会社 半導体静電保護素子及びその製造方法
DE19856128A1 (de) 1998-12-04 2000-06-15 Volkswagen Ag Verfahren und Einrichtung zum Lesen von Navigationsdaten
US6051456A (en) * 1998-12-21 2000-04-18 Motorola, Inc. Semiconductor component and method of manufacture
DE602005019244D1 (de) * 2005-11-25 2010-03-25 St Microelectronics Srl Transistorstruktur mit hoher Eingangsimpedanz und hohem Stromvermögen und zugehöriges Herstellungsverfahren
US9601607B2 (en) * 2013-11-27 2017-03-21 Qualcomm Incorporated Dual mode transistor

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3650186T2 (de) * 1985-01-30 1995-05-24 Toshiba Kawasaki Kk Halbleiteranordnung und Verfahren zu deren Herstellung.
US4786961A (en) * 1986-02-28 1988-11-22 General Electric Company Bipolar transistor with transient suppressor
US4868135A (en) * 1988-12-21 1989-09-19 International Business Machines Corporation Method for manufacturing a Bi-CMOS device

Also Published As

Publication number Publication date
DE69221966T2 (de) 1998-03-12
US5101257A (en) 1992-03-31
EP0521702A1 (de) 1993-01-07
EP0521702B1 (de) 1997-09-03
KR930003371A (ko) 1993-02-24
KR100227710B1 (ko) 1999-11-01
JPH05190780A (ja) 1993-07-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee