DE69205938T2 - Verfahren zur Bildung einer Nitridschicht mit Benutzung von vorgewärmtem Ammoniak. - Google Patents

Verfahren zur Bildung einer Nitridschicht mit Benutzung von vorgewärmtem Ammoniak.

Info

Publication number
DE69205938T2
DE69205938T2 DE69205938T DE69205938T DE69205938T2 DE 69205938 T2 DE69205938 T2 DE 69205938T2 DE 69205938 T DE69205938 T DE 69205938T DE 69205938 T DE69205938 T DE 69205938T DE 69205938 T2 DE69205938 T2 DE 69205938T2
Authority
DE
Germany
Prior art keywords
forming
nitride layer
preheated ammonia
preheated
ammonia
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69205938T
Other languages
English (en)
Other versions
DE69205938D1 (de
Inventor
Stanley M Filipiak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE69205938D1 publication Critical patent/DE69205938D1/de
Application granted granted Critical
Publication of DE69205938T2 publication Critical patent/DE69205938T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3211—Nitridation of silicon-containing layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Vapour Deposition (AREA)
  • Solid-Phase Diffusion Into Metallic Material Surfaces (AREA)
  • Formation Of Insulating Films (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69205938T 1991-08-26 1992-08-20 Verfahren zur Bildung einer Nitridschicht mit Benutzung von vorgewärmtem Ammoniak. Expired - Fee Related DE69205938T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/749,820 US5188979A (en) 1991-08-26 1991-08-26 Method for forming a nitride layer using preheated ammonia

Publications (2)

Publication Number Publication Date
DE69205938D1 DE69205938D1 (de) 1995-12-14
DE69205938T2 true DE69205938T2 (de) 1996-05-30

Family

ID=25015348

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69205938T Expired - Fee Related DE69205938T2 (de) 1991-08-26 1992-08-20 Verfahren zur Bildung einer Nitridschicht mit Benutzung von vorgewärmtem Ammoniak.

Country Status (5)

Country Link
US (1) US5188979A (de)
EP (1) EP0535354B1 (de)
JP (1) JP3303144B2 (de)
KR (1) KR100285139B1 (de)
DE (1) DE69205938T2 (de)

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US5478780A (en) * 1990-03-30 1995-12-26 Siemens Aktiengesellschaft Method and apparatus for producing conductive layers or structures for VLSI circuits
US5652181A (en) * 1993-11-10 1997-07-29 Micron Display Technology, Inc. Thermal process for forming high value resistors
SG165131A1 (en) * 1994-01-27 2010-10-28 Insync Systems Inc Moisture removal in semiconductor processing
US5504041A (en) * 1994-08-01 1996-04-02 Texas Instruments Incorporated Conductive exotic-nitride barrier layer for high-dielectric-constant materials
US5552340A (en) * 1995-10-27 1996-09-03 Vanguard International Semiconductor Corp. Nitridation of titanium, for use with tungsten filled contact holes
US6204171B1 (en) 1996-05-24 2001-03-20 Micron Technology, Inc. Process for forming a film composed of a nitride of a diffusion barrier material
US5633200A (en) * 1996-05-24 1997-05-27 Micron Technology, Inc. Process for manufacturing a large grain tungsten nitride film and process for manufacturing a lightly nitrided titanium salicide diffusion barrier with a large grain tungsten nitride cover layer
US5759916A (en) * 1996-06-24 1998-06-02 Taiwan Semiconductor Manufacturing Company Ltd Method for forming a void-free titanium nitride anti-reflective coating(ARC) layer upon an aluminum containing conductor layer
US5801097A (en) * 1997-03-10 1998-09-01 Vanguard International Semiconductor Corporation Thermal annealing method employing activated nitrogen for forming nitride layers
US6475927B1 (en) * 1998-02-02 2002-11-05 Micron Technology, Inc. Method of forming a semiconductor device
US6391760B1 (en) * 1998-12-08 2002-05-21 United Microelectronics Corp. Method of fabricating local interconnect
US6146991A (en) * 1999-09-03 2000-11-14 Taiwan Semiconductor Manufacturing Company Barrier metal composite layer featuring a thin plasma vapor deposited titanium nitride capping layer
DE19958200B4 (de) * 1999-12-02 2006-07-06 Infineon Technologies Ag Mikroelektronische Struktur und Verfahren zu deren Herstellung
US6451692B1 (en) * 2000-08-18 2002-09-17 Micron Technology, Inc. Preheating of chemical vapor deposition precursors
US6806095B2 (en) * 2002-03-06 2004-10-19 Padmapani C. Nallan Method of plasma etching of high-K dielectric materials with high selectivity to underlying layers
US20060252265A1 (en) * 2002-03-06 2006-11-09 Guangxiang Jin Etching high-kappa dielectric materials with good high-kappa foot control and silicon recess control
US7094704B2 (en) * 2002-05-09 2006-08-22 Applied Materials, Inc. Method of plasma etching of high-K dielectric materials
US6902681B2 (en) * 2002-06-26 2005-06-07 Applied Materials Inc Method for plasma etching of high-K dielectric materials
US20040007561A1 (en) * 2002-07-12 2004-01-15 Applied Materials, Inc. Method for plasma etching of high-K dielectric materials
US6855643B2 (en) * 2002-07-12 2005-02-15 Padmapani C. Nallan Method for fabricating a gate structure
US20060102197A1 (en) * 2004-11-16 2006-05-18 Kang-Lie Chiang Post-etch treatment to remove residues
US7368394B2 (en) * 2006-02-27 2008-05-06 Applied Materials, Inc. Etch methods to form anisotropic features for high aspect ratio applications
US20070202700A1 (en) * 2006-02-27 2007-08-30 Applied Materials, Inc. Etch methods to form anisotropic features for high aspect ratio applications
US7846845B2 (en) * 2006-10-26 2010-12-07 Applied Materials, Inc. Integrated method for removal of halogen residues from etched substrates in a processing system
US7655571B2 (en) * 2006-10-26 2010-02-02 Applied Materials, Inc. Integrated method and apparatus for efficient removal of halogen residues from etched substrates
US7946759B2 (en) * 2007-02-16 2011-05-24 Applied Materials, Inc. Substrate temperature measurement by infrared transmission
US20080203056A1 (en) * 2007-02-26 2008-08-28 Judy Wang Methods for etching high aspect ratio features
JP2009021584A (ja) * 2007-06-27 2009-01-29 Applied Materials Inc 高ｋ材料ゲート構造の高温エッチング方法
US20100330805A1 (en) * 2007-11-02 2010-12-30 Kenny Linh Doan Methods for forming high aspect ratio features on a substrate
US10453694B2 (en) 2011-03-01 2019-10-22 Applied Materials, Inc. Abatement and strip process chamber in a dual loadlock configuration
US8992689B2 (en) 2011-03-01 2015-03-31 Applied Materials, Inc. Method for removing halogen-containing residues from substrate
US8845816B2 (en) 2011-03-01 2014-09-30 Applied Materials, Inc. Method extending the service interval of a gas distribution plate
US10090181B2 (en) 2011-03-01 2018-10-02 Applied Materials, Inc. Method and apparatus for substrate transfer and radical confinement
US11171008B2 (en) 2011-03-01 2021-11-09 Applied Materials, Inc. Abatement and strip process chamber in a dual load lock configuration
US9533332B2 (en) 2011-10-06 2017-01-03 Applied Materials, Inc. Methods for in-situ chamber clean utilized in an etching processing chamber
WO2013130191A1 (en) 2012-02-29 2013-09-06 Applied Materials, Inc. Abatement and strip process chamber in a load lock configuration
US8932947B1 (en) 2013-07-23 2015-01-13 Applied Materials, Inc. Methods for forming a round bottom silicon trench recess for semiconductor applications
US9214377B2 (en) 2013-10-31 2015-12-15 Applied Materials, Inc. Methods for silicon recess structures in a substrate by utilizing a doping layer

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4524718A (en) * 1982-11-22 1985-06-25 Gordon Roy G Reactor for continuous coating of glass
US4920071A (en) * 1985-03-15 1990-04-24 Fairchild Camera And Instrument Corporation High temperature interconnect system for an integrated circuit
US4784973A (en) * 1987-08-24 1988-11-15 Inmos Corporation Semiconductor contact silicide/nitride process with control for silicide thickness
NL8800359A (nl) * 1988-02-15 1989-09-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
GB8809651D0 (en) * 1988-04-23 1988-05-25 Tioxide Group Plc Nitrogen compounds
US5084417A (en) * 1989-01-06 1992-01-28 International Business Machines Corporation Method for selective deposition of refractory metals on silicon substrates and device formed thereby
GB8913106D0 (en) * 1989-06-07 1989-07-26 Tioxide Group Plc Production of nitrogen compounds
US5043300A (en) * 1990-04-16 1991-08-27 Applied Materials, Inc. Single anneal step process for forming titanium silicide on semiconductor wafer

Also Published As

Publication number Publication date
DE69205938D1 (de) 1995-12-14
EP0535354A1 (de) 1993-04-07
JP3303144B2 (ja) 2002-07-15
US5188979A (en) 1993-02-23
JPH05302160A (ja) 1993-11-16
EP0535354B1 (de) 1995-11-08
KR100285139B1 (ko) 2001-04-02
KR930005137A (ko) 1993-03-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8327 Change in the person/name/address of the patent owner

Owner name: FREESCALE SEMICONDUCTOR, INC. (N.D.GES.D. STAATES

8339 Ceased/non-payment of the annual fee