DE69205239D1 - Via-Loch Struktur und Verfahren. - Google Patents

Via-Loch Struktur und Verfahren.

Info

Publication number
DE69205239D1
DE69205239D1 DE69205239T DE69205239T DE69205239D1 DE 69205239 D1 DE69205239 D1 DE 69205239D1 DE 69205239 T DE69205239 T DE 69205239T DE 69205239 T DE69205239 T DE 69205239T DE 69205239 D1 DE69205239 D1 DE 69205239D1
Authority
DE
Germany
Prior art keywords
procedure
hole structure
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69205239T
Other languages
English (en)
Other versions
DE69205239T2 (de
Inventor
Motoaki Tani
Shoichi Miyahara
Makoto Sasaki
Eiji Horikoshi
Isao Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=16290927&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69205239(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69205239D1 publication Critical patent/DE69205239D1/de
Publication of DE69205239T2 publication Critical patent/DE69205239T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
DE69205239T 1991-08-01 1992-07-31 Via-Loch Struktur und Verfahren. Expired - Fee Related DE69205239T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3192414A JP2920854B2 (ja) 1991-08-01 1991-08-01 ビィアホール構造及びその形成方法

Publications (2)

Publication Number Publication Date
DE69205239D1 true DE69205239D1 (de) 1995-11-09
DE69205239T2 DE69205239T2 (de) 1996-03-14

Family

ID=16290927

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69205239T Expired - Fee Related DE69205239T2 (de) 1991-08-01 1992-07-31 Via-Loch Struktur und Verfahren.

Country Status (5)

Country Link
US (1) US5308929A (de)
EP (1) EP0526243B1 (de)
JP (1) JP2920854B2 (de)
KR (1) KR960006986B1 (de)
DE (1) DE69205239T2 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NO173278C (no) * 1986-05-21 1993-12-01 Research Corp Analogifremgangsm}te for fremstilling av terapeutisk aktive 5-androsten-17-on-derivater
US5414221A (en) 1991-12-31 1995-05-09 Intel Corporation Embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias
US5973910A (en) * 1991-12-31 1999-10-26 Intel Corporation Decoupling capacitor in an integrated circuit
US5285017A (en) * 1991-12-31 1994-02-08 Intel Corporation Embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias
US5472900A (en) * 1991-12-31 1995-12-05 Intel Corporation Capacitor fabricated on a substrate containing electronic circuitry
DE59403626D1 (de) * 1993-09-29 1997-09-11 Siemens Nv Verfahren zur Herstellung einer zwei- oder mehrlagigen Verdrahtung und danach hergestellte zwei- oder mehrlagige Verdrahtung
JP2571677B2 (ja) * 1994-11-22 1997-01-16 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体装置の製造方法
US5960315A (en) * 1997-07-10 1999-09-28 International Business Machines Corporation Tapered via using sidewall spacer reflow
US6054768A (en) * 1997-10-02 2000-04-25 Micron Technology, Inc. Metal fill by treatment of mobility layers
US6175087B1 (en) 1998-12-02 2001-01-16 International Business Machines Corporation Composite laminate circuit structure and method of forming the same
US6569604B1 (en) 1999-06-30 2003-05-27 International Business Machines Corporation Blind via formation in a photoimageable dielectric material
JP2001267747A (ja) * 2000-03-22 2001-09-28 Nitto Denko Corp 多層回路基板の製造方法
KR100509058B1 (ko) * 2000-04-11 2005-08-18 엘지전자 주식회사 인쇄회로기판의 제조방법
JP3757143B2 (ja) * 2001-10-11 2006-03-22 富士通株式会社 半導体装置の製造方法及び半導体装置
US7060624B2 (en) * 2003-08-13 2006-06-13 International Business Machines Corporation Deep filled vias
JP5010948B2 (ja) * 2007-03-06 2012-08-29 オリンパス株式会社 半導体装置
KR101095409B1 (ko) * 2007-07-25 2011-12-19 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치
JP2009200356A (ja) * 2008-02-22 2009-09-03 Tdk Corp プリント配線板及びその製造方法
WO2010072246A1 (en) * 2008-12-22 2010-07-01 Interuniversitair Microelektronica Centrum Vzw Method for resist development in narrow high aspect ratio vias
KR101006603B1 (ko) * 2009-01-09 2011-01-07 삼성전기주식회사 인쇄회로기판 및 그 제조방법
TWI392425B (zh) * 2009-08-25 2013-04-01 Unimicron Technology Corp 內埋式線路板及其製造方法
JP7366025B2 (ja) * 2018-07-31 2023-10-20 京セラ株式会社 印刷配線板及び印刷配線板の製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3348990A (en) * 1963-12-23 1967-10-24 Sperry Rand Corp Process for electrically interconnecting elements on different layers of a multilayer printed circuit assembly
US3617613A (en) * 1968-10-17 1971-11-02 Spaulding Fibre Co Punchable printed circuit board base
US4897627A (en) * 1985-06-21 1990-01-30 Magnetek Universal Mfg. Corp. Fluorescent ballast assembly including a strip circuit board
US4994410A (en) * 1988-04-04 1991-02-19 Motorola, Inc. Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process
JPH0783168B2 (ja) * 1988-04-13 1995-09-06 株式会社日立製作所 プリント板の製造方法
US5001605A (en) * 1988-11-30 1991-03-19 Hughes Aircraft Company Multilayer printed wiring board with single layer vias
JP2551203B2 (ja) * 1990-06-05 1996-11-06 三菱電機株式会社 半導体装置
US5113315A (en) * 1990-08-07 1992-05-12 Cirqon Technologies Corporation Heat-conductive metal ceramic composite material panel system for improved heat dissipation

Also Published As

Publication number Publication date
KR960006986B1 (ko) 1996-05-25
EP0526243A1 (de) 1993-02-03
JP2920854B2 (ja) 1999-07-19
US5308929A (en) 1994-05-03
DE69205239T2 (de) 1996-03-14
EP0526243B1 (de) 1995-10-04
JPH0537158A (ja) 1993-02-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee