DE69132584D1 - Speicherzugriffsystem und Verfahren - Google Patents

Speicherzugriffsystem und Verfahren

Info

Publication number
DE69132584D1
DE69132584D1 DE69132584T DE69132584T DE69132584D1 DE 69132584 D1 DE69132584 D1 DE 69132584D1 DE 69132584 T DE69132584 T DE 69132584T DE 69132584 T DE69132584 T DE 69132584T DE 69132584 D1 DE69132584 D1 DE 69132584D1
Authority
DE
Germany
Prior art keywords
memory access
access system
memory
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69132584T
Other languages
English (en)
Other versions
DE69132584T2 (de
Inventor
Hideyuki Iino
Hiromasa Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69132584D1 publication Critical patent/DE69132584D1/de
Application granted granted Critical
Publication of DE69132584T2 publication Critical patent/DE69132584T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Information Transfer Systems (AREA)
  • Complex Calculations (AREA)
DE69132584T 1990-08-24 1991-08-23 Speicherzugriffsystem und Verfahren Expired - Fee Related DE69132584T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP22277490A JP3215105B2 (ja) 1990-08-24 1990-08-24 メモリアクセス装置
PCT/JP1991/001124 WO1992003791A1 (en) 1990-08-24 1991-08-23 Memory access system

Publications (2)

Publication Number Publication Date
DE69132584D1 true DE69132584D1 (de) 2001-05-23
DE69132584T2 DE69132584T2 (de) 2001-08-09

Family

ID=16787680

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69132584T Expired - Fee Related DE69132584T2 (de) 1990-08-24 1991-08-23 Speicherzugriffsystem und Verfahren

Country Status (6)

Country Link
US (1) US5586282A (de)
EP (1) EP0497986B1 (de)
JP (1) JP3215105B2 (de)
KR (1) KR970008600B1 (de)
DE (1) DE69132584T2 (de)
WO (1) WO1992003791A1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3193525B2 (ja) * 1993-05-31 2001-07-30 キヤノン株式会社 情報処理装置
JPH07104944A (ja) * 1993-09-30 1995-04-21 Sony Corp 情報転送装置
US5784705A (en) * 1996-07-15 1998-07-21 Mosys, Incorporated Method and structure for performing pipeline burst accesses in a semiconductor memory
US6212611B1 (en) 1998-11-03 2001-04-03 Intel Corporation Method and apparatus for providing a pipelined memory controller
SE9804529L (sv) * 1998-12-23 2000-06-24 Axis Ab Flexibel minneskanal
US7051264B2 (en) * 2001-11-14 2006-05-23 Monolithic System Technology, Inc. Error correcting memory and method of operating same
US6824936B1 (en) 2003-08-05 2004-11-30 Eastman Kodak Company Hindered amine light stabilizer for improved yellow dark stability
US7246215B2 (en) * 2003-11-26 2007-07-17 Intel Corporation Systolic memory arrays
US7392456B2 (en) * 2004-11-23 2008-06-24 Mosys, Inc. Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory
KR101645003B1 (ko) * 2010-02-12 2016-08-03 삼성전자주식회사 메모리 제어기 및 그 메모리 제어기가 탑재된 컴퓨팅 장치

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6057090B2 (ja) * 1980-09-19 1985-12-13 株式会社日立製作所 データ記憶装置およびそれを用いた処理装置
JPS6057447A (ja) * 1983-09-09 1985-04-03 Nec Corp メモリアクセス制御方式
JPS618785A (ja) * 1984-06-21 1986-01-16 Fujitsu Ltd 記憶装置アクセス制御方式
JPS61294581A (ja) * 1985-06-22 1986-12-25 Nec Corp メモリアクセス制御装置
US4791552A (en) * 1986-01-29 1988-12-13 Digital Equipment Corporation Apparatus and method for addressing semiconductor arrays in a main memory unit on consecutive system clock cycles
JPH0731669B2 (ja) * 1986-04-04 1995-04-10 株式会社日立製作所 ベクトル・プロセツサ
US4851990A (en) * 1987-02-09 1989-07-25 Advanced Micro Devices, Inc. High performance processor interface between a single chip processor and off chip memory means having a dedicated and shared bus structure
JPS63308656A (ja) * 1987-06-10 1988-12-16 Fujitsu Ltd ブロックアクセス制御装置
JPH01152547A (ja) * 1987-12-09 1989-06-15 Fujitsu Ltd 記憶装置の読み出し制御回路
JPH0619737B2 (ja) * 1988-05-13 1994-03-16 株式会社東芝 メモリアクセス装置
US5125084A (en) * 1988-05-26 1992-06-23 Ibm Corporation Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller
JPH0657447A (ja) * 1992-08-10 1994-03-01 Sumitomo Metal Ind Ltd 耐チッピング性に優れた自動車外装用鋼板

Also Published As

Publication number Publication date
EP0497986A4 (en) 1993-02-24
JP3215105B2 (ja) 2001-10-02
JPH04105149A (ja) 1992-04-07
KR920702512A (ko) 1992-09-04
EP0497986B1 (de) 2001-04-18
DE69132584T2 (de) 2001-08-09
KR970008600B1 (en) 1997-05-27
EP0497986A1 (de) 1992-08-12
US5586282A (en) 1996-12-17
WO1992003791A1 (en) 1992-03-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee