SE9804529L - Flexibel minneskanal - Google Patents

Flexibel minneskanal

Info

Publication number
SE9804529L
SE9804529L SE9804529A SE9804529A SE9804529L SE 9804529 L SE9804529 L SE 9804529L SE 9804529 A SE9804529 A SE 9804529A SE 9804529 A SE9804529 A SE 9804529A SE 9804529 L SE9804529 L SE 9804529L
Authority
SE
Sweden
Prior art keywords
memory channel
memory
data
channel
different blocks
Prior art date
Application number
SE9804529A
Other languages
English (en)
Other versions
SE9804529D0 (sv
Inventor
Stefan Sandstroem
Stefan Lundberg
Original Assignee
Axis Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Axis Ab filed Critical Axis Ab
Priority to SE9804529A priority Critical patent/SE9804529L/sv
Publication of SE9804529D0 publication Critical patent/SE9804529D0/sv
Priority to US09/252,173 priority patent/US6381687B2/en
Priority to CNB998163481A priority patent/CN100338585C/zh
Priority to EP99965639A priority patent/EP1141837B1/en
Priority to AU21331/00A priority patent/AU2133100A/en
Priority to PCT/SE1999/002339 priority patent/WO2000039685A1/en
Priority to JP2000591513A priority patent/JP4584457B2/ja
Publication of SE9804529L publication Critical patent/SE9804529L/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Image Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Information Transfer Systems (AREA)
SE9804529A 1998-12-23 1998-12-23 Flexibel minneskanal SE9804529L (sv)

Priority Applications (7)

Application Number Priority Date Filing Date Title
SE9804529A SE9804529L (sv) 1998-12-23 1998-12-23 Flexibel minneskanal
US09/252,173 US6381687B2 (en) 1998-12-23 1999-02-18 Flexible memory channel
CNB998163481A CN100338585C (zh) 1998-12-23 1999-12-14 用于数据传输的方法和装置
EP99965639A EP1141837B1 (en) 1998-12-23 1999-12-14 Flexible memory channel
AU21331/00A AU2133100A (en) 1998-12-23 1999-12-14 Flexible memory channel
PCT/SE1999/002339 WO2000039685A1 (en) 1998-12-23 1999-12-14 Flexible memory channel
JP2000591513A JP4584457B2 (ja) 1998-12-23 1999-12-14 フレキシブルメモリチャネル

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9804529A SE9804529L (sv) 1998-12-23 1998-12-23 Flexibel minneskanal

Publications (2)

Publication Number Publication Date
SE9804529D0 SE9804529D0 (sv) 1998-12-23
SE9804529L true SE9804529L (sv) 2000-06-24

Family

ID=20413846

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9804529A SE9804529L (sv) 1998-12-23 1998-12-23 Flexibel minneskanal

Country Status (7)

Country Link
US (1) US6381687B2 (sv)
EP (1) EP1141837B1 (sv)
JP (1) JP4584457B2 (sv)
CN (1) CN100338585C (sv)
AU (1) AU2133100A (sv)
SE (1) SE9804529L (sv)
WO (1) WO2000039685A1 (sv)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
US9552047B2 (en) 2001-03-05 2017-01-24 Pact Xpp Technologies Ag Multiprocessor having runtime adjustable clock and clock dependent power supply
US9436631B2 (en) * 2001-03-05 2016-09-06 Pact Xpp Technologies Ag Chip including memory element storing higher level memory data on a page by page basis
US9170812B2 (en) 2002-03-21 2015-10-27 Pact Xpp Technologies Ag Data processing system having integrated pipelined array data processor
US7140019B2 (en) * 2002-06-28 2006-11-21 Motorola, Inc. Scheduler of program instructions for streaming vector processor having interconnected functional units
US7415601B2 (en) * 2002-06-28 2008-08-19 Motorola, Inc. Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters
US7159099B2 (en) * 2002-06-28 2007-01-02 Motorola, Inc. Streaming vector processor with reconfigurable interconnection switch
US6941438B2 (en) * 2003-01-10 2005-09-06 Intel Corporation Memory interleaving
US7290122B2 (en) * 2003-08-29 2007-10-30 Motorola, Inc. Dataflow graph compression for power reduction in a vector processor
US7610466B2 (en) * 2003-09-05 2009-10-27 Freescale Semiconductor, Inc. Data processing system using independent memory and register operand size specifiers and method thereof
US7315932B2 (en) * 2003-09-08 2008-01-01 Moyer William C Data processing system having instruction specifiers for SIMD register operands and method thereof
US7107436B2 (en) * 2003-09-08 2006-09-12 Freescale Semiconductor, Inc. Conditional next portion transferring of data stream to or from register based on subsequent instruction aspect
US7275148B2 (en) * 2003-09-08 2007-09-25 Freescale Semiconductor, Inc. Data processing system using multiple addressing modes for SIMD operations and method thereof
US7634633B2 (en) * 2006-11-30 2009-12-15 Motorola, Inc. Method and apparatus for memory address generation using dynamic stream descriptors
US7945768B2 (en) * 2008-06-05 2011-05-17 Motorola Mobility, Inc. Method and apparatus for nested instruction looping using implicit predicates

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4547849A (en) * 1981-12-09 1985-10-15 Glenn Louie Interface between a microprocessor and a coprocessor
JPH02287750A (ja) * 1989-04-28 1990-11-27 Toshiba Corp チャネル装置におけるアドレス変換方式
JP3215105B2 (ja) * 1990-08-24 2001-10-02 富士通株式会社 メモリアクセス装置
JPH06103213A (ja) * 1992-09-18 1994-04-15 Hitachi Ltd 入出力装置
JP3206215B2 (ja) * 1993-05-25 2001-09-10 松下電器産業株式会社 ディジタル信号処理装置
GB2304438A (en) * 1995-08-17 1997-03-19 Kenneth Austin Re-configurable application specific device
US5911153A (en) * 1996-10-03 1999-06-08 International Business Machines Corporation Memory design which facilitates incremental fetch and store requests off applied base address requests
US6055622A (en) * 1997-02-03 2000-04-25 Intel Corporation Global stride prefetching apparatus and method for a high-performance processor
US5940876A (en) * 1997-04-02 1999-08-17 Advanced Micro Devices, Inc. Stride instruction for fetching data separated by a stride amount

Also Published As

Publication number Publication date
CN100338585C (zh) 2007-09-19
AU2133100A (en) 2000-07-31
WO2000039685A1 (en) 2000-07-06
SE9804529D0 (sv) 1998-12-23
US20020019905A1 (en) 2002-02-14
EP1141837A1 (en) 2001-10-10
JP4584457B2 (ja) 2010-11-24
US6381687B2 (en) 2002-04-30
JP2002533833A (ja) 2002-10-08
EP1141837B1 (en) 2013-03-20
CN1335963A (zh) 2002-02-13

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