DE69129617D1 - Integrierte Schaltungsanordnung, insbesondere geeignet für Hochspannungsanwendungen - Google Patents
Integrierte Schaltungsanordnung, insbesondere geeignet für HochspannungsanwendungenInfo
- Publication number
- DE69129617D1 DE69129617D1 DE69129617T DE69129617T DE69129617D1 DE 69129617 D1 DE69129617 D1 DE 69129617D1 DE 69129617 T DE69129617 T DE 69129617T DE 69129617 T DE69129617 T DE 69129617T DE 69129617 D1 DE69129617 D1 DE 69129617D1
- Authority
- DE
- Germany
- Prior art keywords
- integrated circuit
- particularly suitable
- circuit arrangement
- voltage applications
- applications
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/765—Making of isolation regions between components by field effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
- H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/628,307 US5113236A (en) | 1990-12-14 | 1990-12-14 | Integrated circuit device particularly adapted for high voltage applications |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69129617D1 true DE69129617D1 (de) | 1998-07-23 |
DE69129617T2 DE69129617T2 (de) | 1999-01-28 |
Family
ID=24518339
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69129617T Expired - Fee Related DE69129617T2 (de) | 1990-12-14 | 1991-12-06 | Integrierte Schaltungsanordnung, insbesondere geeignet für Hochspannungsanwendungen |
Country Status (5)
Country | Link |
---|---|
US (1) | US5113236A (de) |
EP (1) | EP0490437B1 (de) |
JP (1) | JP3423006B2 (de) |
KR (1) | KR100257412B1 (de) |
DE (1) | DE69129617T2 (de) |
Families Citing this family (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5621239A (en) * | 1990-11-05 | 1997-04-15 | Fujitsu Limited | SOI device having a buried layer of reduced resistivity |
DE69209678T2 (de) * | 1991-02-01 | 1996-10-10 | Philips Electronics Nv | Halbleiteranordnung für Hochspannungsverwendung und Verfahren zur Herstellung |
US5246870A (en) * | 1991-02-01 | 1993-09-21 | North American Philips Corporation | Method for making an improved high voltage thin film transistor having a linear doping profile |
JP2654268B2 (ja) * | 1991-05-13 | 1997-09-17 | 株式会社東芝 | 半導体装置の使用方法 |
EP0562271B1 (de) * | 1992-03-26 | 1998-01-14 | Texas Instruments Incorporated | Hochspannungstruktur mit oxydisolierter Source und RESURF-Drift-Zone in Massivsilizium |
JPH08501900A (ja) * | 1992-06-17 | 1996-02-27 | ハリス・コーポレーション | 結合ウェーハの製法 |
DE4233773C2 (de) * | 1992-10-07 | 1996-09-19 | Daimler Benz Ag | Halbleiterstruktur für Halbleiterbauelemente mit hoher Durchbruchspannung |
EP0610599A1 (de) * | 1993-01-04 | 1994-08-17 | Texas Instruments Incorporated | Hochspannungstransistor mit Drift-Zone |
US5548150A (en) * | 1993-03-10 | 1996-08-20 | Kabushiki Kaisha Toshiba | Field effect transistor |
US5373183A (en) * | 1993-04-28 | 1994-12-13 | Harris Corporation | Integrated circuit with improved reverse bias breakdown |
DE69417944T2 (de) * | 1993-04-30 | 1999-12-09 | International Business Machines Corp., Armonk | Verfahren zum Herstellen einer Schutzdiode gegen elektrostatische Entladungen in der Silizium-auf-Insulator-Technologie |
US5378912A (en) * | 1993-11-10 | 1995-01-03 | Philips Electronics North America Corporation | Lateral semiconductor-on-insulator (SOI) semiconductor device having a lateral drift region |
US5382818A (en) * | 1993-12-08 | 1995-01-17 | Philips Electronics North America Corporation | Lateral semiconductor-on-insulator (SOI) semiconductor device having a buried diode |
JPH0923017A (ja) * | 1995-07-06 | 1997-01-21 | Mitsubishi Electric Corp | Soi入力保護回路 |
US5648671A (en) * | 1995-12-13 | 1997-07-15 | U S Philips Corporation | Lateral thin-film SOI devices with linearly-graded field oxide and linear doping profile |
JP2822961B2 (ja) * | 1995-12-14 | 1998-11-11 | 日本電気株式会社 | 半導体装置 |
JP3575908B2 (ja) * | 1996-03-28 | 2004-10-13 | 株式会社東芝 | 半導体装置 |
US6121661A (en) * | 1996-12-11 | 2000-09-19 | International Business Machines Corporation | Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation |
US6034399A (en) * | 1997-03-06 | 2000-03-07 | Lockheed Martin Corporation | Electrostatic discharge protection for silicon-on-insulator |
US6160292A (en) * | 1997-04-23 | 2000-12-12 | International Business Machines Corporation | Circuit and methods to improve the operation of SOI devices |
DE19741928C1 (de) * | 1997-09-10 | 1998-09-24 | Siemens Ag | Halbleiterbauelement |
JP3061020B2 (ja) | 1997-11-12 | 2000-07-10 | 日本電気株式会社 | 誘電体分離型半導体装置 |
JPH11261010A (ja) * | 1998-03-13 | 1999-09-24 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US5877048A (en) * | 1998-03-23 | 1999-03-02 | Texas Instruments--Acer Incorporated | 3-D CMOS transistors with high ESD reliability |
JPH11354631A (ja) * | 1998-06-11 | 1999-12-24 | Nec Kansai Ltd | 半導体装置 |
US6621121B2 (en) | 1998-10-26 | 2003-09-16 | Silicon Semiconductor Corporation | Vertical MOSFETs having trench-based gate electrodes within deeper trench-based source electrodes |
US6545316B1 (en) | 2000-06-23 | 2003-04-08 | Silicon Wireless Corporation | MOSFET devices having linear transfer characteristics when operating in velocity saturation mode and methods of forming and operating same |
US6521947B1 (en) * | 1999-01-28 | 2003-02-18 | International Business Machines Corporation | Method of integrating substrate contact on SOI wafers with STI process |
US6781194B2 (en) * | 2001-04-11 | 2004-08-24 | Silicon Semiconductor Corporation | Vertical power devices having retrograded-doped transition regions and insulated trench-based electrodes therein |
US6784486B2 (en) * | 2000-06-23 | 2004-08-31 | Silicon Semiconductor Corporation | Vertical power devices having retrograded-doped transition regions therein |
US6512269B1 (en) | 2000-09-07 | 2003-01-28 | International Business Machines Corporation | High-voltage high-speed SOI MOSFET |
EP1396030B1 (de) * | 2001-04-11 | 2011-06-29 | Silicon Semiconductor Corporation | Vertikale Leistungshalbleiteranordnung und Verfahren zu deren Herstellung |
JP5151087B2 (ja) * | 2005-11-01 | 2013-02-27 | 株式会社デンソー | 半導体装置およびその製造方法 |
US10062788B2 (en) * | 2008-07-30 | 2018-08-28 | Maxpower Semiconductor Inc. | Semiconductor on insulator devices containing permanent charge |
JP2009060064A (ja) * | 2007-09-04 | 2009-03-19 | New Japan Radio Co Ltd | 半導体装置及びその製造方法 |
JP5132481B2 (ja) * | 2008-08-27 | 2013-01-30 | 株式会社日立製作所 | 半導体集積回路装置 |
US7829947B2 (en) * | 2009-03-17 | 2010-11-09 | Alpha & Omega Semiconductor Incorporated | Bottom-drain LDMOS power MOSFET structure having a top drain strap |
US10529866B2 (en) * | 2012-05-30 | 2020-01-07 | X-Fab Semiconductor Foundries Gmbh | Semiconductor device |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3701198A (en) * | 1970-08-14 | 1972-10-31 | Bell Telephone Labor Inc | Monolithic integrated circuit structures and methods of making same |
US4883543A (en) * | 1980-06-05 | 1989-11-28 | Texas Instruments Incroporated | Shielding for implant in manufacture of dynamic memory |
JPS6271275A (ja) * | 1985-09-25 | 1987-04-01 | Toshiba Corp | 半導体集積回路 |
JPS63157475A (ja) * | 1986-12-20 | 1988-06-30 | Toshiba Corp | 半導体装置及びその製造方法 |
JPS6446979A (en) * | 1987-08-14 | 1989-02-21 | Oki Electric Ind Co Ltd | Analogue switch and sample-and-hold circuit with analogue switch |
JPH01238066A (ja) * | 1988-03-18 | 1989-09-22 | Fujitsu Ltd | 高耐圧トランジスタ |
-
1990
- 1990-12-14 US US07/628,307 patent/US5113236A/en not_active Expired - Lifetime
-
1991
- 1991-12-06 DE DE69129617T patent/DE69129617T2/de not_active Expired - Fee Related
- 1991-12-06 EP EP91203189A patent/EP0490437B1/de not_active Expired - Lifetime
- 1991-12-11 KR KR1019910022656A patent/KR100257412B1/ko not_active IP Right Cessation
- 1991-12-13 JP JP33071191A patent/JP3423006B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR100257412B1 (ko) | 2000-05-15 |
DE69129617T2 (de) | 1999-01-28 |
EP0490437A1 (de) | 1992-06-17 |
KR920013780A (ko) | 1992-07-29 |
EP0490437B1 (de) | 1998-06-17 |
JPH04275450A (ja) | 1992-10-01 |
JP3423006B2 (ja) | 2003-07-07 |
US5113236A (en) | 1992-05-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N |
|
8320 | Willingness to grant licences declared (paragraph 23) | ||
8328 | Change in the person/name/address of the agent |
Representative=s name: VOLMER, G., DIPL.-ING., PAT.-ANW., 52066 AACHEN |
|
8339 | Ceased/non-payment of the annual fee |