DE69126076D1 - Verbundswafer und Verfahren zu dessen Herstellung - Google Patents

Verbundswafer und Verfahren zu dessen Herstellung

Info

Publication number
DE69126076D1
DE69126076D1 DE69126076T DE69126076T DE69126076D1 DE 69126076 D1 DE69126076 D1 DE 69126076D1 DE 69126076 T DE69126076 T DE 69126076T DE 69126076 T DE69126076 T DE 69126076T DE 69126076 D1 DE69126076 D1 DE 69126076D1
Authority
DE
Germany
Prior art keywords
manufacture
composite wafer
wafer
composite
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69126076T
Other languages
English (en)
Other versions
DE69126076T2 (de
Inventor
Nobuyoshi Ogino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Engineering Co Ltd
Original Assignee
Shin Etsu Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Engineering Co Ltd filed Critical Shin Etsu Engineering Co Ltd
Publication of DE69126076D1 publication Critical patent/DE69126076D1/de
Application granted granted Critical
Publication of DE69126076T2 publication Critical patent/DE69126076T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/012—Bonding, e.g. electrostatic for strain gauges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
DE69126076T 1990-09-06 1991-09-02 Verbundswafer und Verfahren zu dessen Herstellung Expired - Fee Related DE69126076T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2236257A JPH0719738B2 (ja) 1990-09-06 1990-09-06 接合ウェーハ及びその製造方法

Publications (2)

Publication Number Publication Date
DE69126076D1 true DE69126076D1 (de) 1997-06-19
DE69126076T2 DE69126076T2 (de) 1997-10-30

Family

ID=16998103

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69126076T Expired - Fee Related DE69126076T2 (de) 1990-09-06 1991-09-02 Verbundswafer und Verfahren zu dessen Herstellung

Country Status (4)

Country Link
US (1) US5238875A (de)
EP (1) EP0475653B1 (de)
JP (1) JPH0719738B2 (de)
DE (1) DE69126076T2 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4115046A1 (de) * 1991-05-08 1992-11-12 Fraunhofer Ges Forschung Direktes substratbonden
DE4133820A1 (de) * 1991-10-12 1993-04-15 Bosch Gmbh Robert Verfahren zur herstellung von halbleiterelementen
DE69333152T2 (de) * 1992-01-30 2004-05-27 Canon K.K. Verfahren zur Herstellung eines Halbleitersubstrates
JPH05218049A (ja) * 1992-01-31 1993-08-27 Nec Corp 半導体素子形成用基板
JP2574594B2 (ja) * 1992-05-26 1997-01-22 松下電器産業株式会社 光導波路素子とその製造方法
JP2574602B2 (ja) * 1992-07-08 1997-01-22 松下電器産業株式会社 光導波路素子
JP2574606B2 (ja) * 1992-09-01 1997-01-22 松下電器産業株式会社 誘電体光導波路素子およびその製造方法
JP2592752B2 (ja) * 1992-10-05 1997-03-19 松下電器産業株式会社 半導体光導波路素子とその製造方法
DE59309969D1 (de) * 1993-05-28 2000-04-13 Ibm Verfahren zur Herstellung eines Plattenstapels aus direkt miteinander verbundenen Siliziumplatten
JPH08255882A (ja) * 1995-03-16 1996-10-01 Komatsu Electron Metals Co Ltd Ｓｏｉ基板の製造方法およびｓｏｉ基板
KR0168348B1 (ko) * 1995-05-11 1999-02-01 김광호 Soi 기판의 제조방법
US6090688A (en) * 1996-11-15 2000-07-18 Komatsu Electronic Metals Co., Ltd. Method for fabricating an SOI substrate
US6413874B1 (en) * 1997-12-26 2002-07-02 Canon Kabushiki Kaisha Method and apparatus for etching a semiconductor article and method of preparing a semiconductor article by using the same
US6054370A (en) * 1998-06-30 2000-04-25 Intel Corporation Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
JP4765157B2 (ja) * 1999-11-17 2011-09-07 株式会社デンソー 半導体基板の製造方法
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
JP2002134721A (ja) * 2000-10-23 2002-05-10 Nec Kyushu Ltd Ｓｏｉウェーハおよびその製造方法
US20050150877A1 (en) * 2002-07-29 2005-07-14 Sumitomo Precision Products Co., Ltd. Method and device for laser beam processing of silicon substrate, and method and device for laser beam cutting of silicon wiring
TW200428637A (en) * 2003-01-23 2004-12-16 Shinetsu Handotai Kk SOI wafer and production method thereof
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
JP4552857B2 (ja) * 2003-09-08 2010-09-29 株式会社Ｓｕｍｃｏ Ｓｏｉウェーハおよびその製造方法
JP2006005341A (ja) * 2004-05-19 2006-01-05 Sumco Corp 貼り合わせｓｏｉ基板およびその製造方法
JP2006134925A (ja) * 2004-11-02 2006-05-25 Nec Electronics Corp Ｓｏｉ基板及びその製造方法
JP5292810B2 (ja) * 2005-12-19 2013-09-18 信越半導体株式会社 Ｓｏｉ基板の製造方法
JP5256625B2 (ja) * 2007-03-05 2013-08-07 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの評価方法
CN112420630B (zh) * 2020-11-23 2024-04-26 西安众力为半导体科技有限公司 一种堆叠键合式igbt器件

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5645047A (en) * 1979-09-20 1981-04-24 Toshiba Corp Manufacture of semiconductor monocrystal film
JPS5680139A (en) * 1979-12-05 1981-07-01 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
JPS5787119A (en) * 1980-11-19 1982-05-31 Toshiba Corp Manufacture of semiconductor device
JPS58180028A (ja) * 1982-04-16 1983-10-21 Oki Electric Ind Co Ltd 半導体ウエハの処理方法
JPS5952841A (ja) * 1982-09-20 1984-03-27 Nec Corp 半導体装置
US4509990A (en) * 1982-11-15 1985-04-09 Hughes Aircraft Company Solid phase epitaxy and regrowth process with controlled defect density profiling for heteroepitaxial semiconductor on insulator composite substrates
JPS6173345A (ja) * 1984-09-19 1986-04-15 Toshiba Corp 半導体装置
NL8501773A (nl) * 1985-06-20 1987-01-16 Philips Nv Werkwijze voor het vervaardigen van halfgeleiderinrichtingen.
JPS6430247A (en) * 1987-07-24 1989-02-01 Fujitsu Ltd Semiconductor device
JP2685819B2 (ja) * 1988-03-31 1997-12-03 株式会社東芝 誘電体分離半導体基板とその製造方法
NL8800953A (nl) * 1988-04-13 1989-11-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderlichaam.
DE3829906A1 (de) * 1988-09-02 1990-03-15 Siemens Ag Verfahren zum herstellen von halbleiter-bauelementen
JPH0355822A (ja) * 1989-07-25 1991-03-11 Shin Etsu Handotai Co Ltd 半導体素子形成用基板の製造方法

Also Published As

Publication number Publication date
JPH0719738B2 (ja) 1995-03-06
EP0475653A2 (de) 1992-03-18
DE69126076T2 (de) 1997-10-30
US5238875A (en) 1993-08-24
EP0475653A3 (de) 1994-03-09
JPH04116816A (ja) 1992-04-17
EP0475653B1 (de) 1997-05-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee